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* Added $dffe support to write_verilogClifford Wolf2014-12-20
* Fixed another bug in write_blif handling of $lut cellsClifford Wolf2014-12-19
* Fixed writing of $lut cells in BLIF backendClifford Wolf2014-12-17
* Added "write_blif -undef" and support for special "-" true/false/undef typeClifford Wolf2014-12-14
* Added "write_blif -blackbox"Clifford Wolf2014-12-14
* Added "blif -unbuf" featureClifford Wolf2014-12-14
* Added log_warning() APIClifford Wolf2014-11-09
* Fixed generation of temp names in verilog backendClifford Wolf2014-11-07
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* namespace YosysClifford Wolf2014-09-27
* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-09-22
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| * Sorting of object names in ilang backendClifford Wolf2014-09-19
| * Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-06
| * Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
| * Removed $bu0 cell typeClifford Wolf2014-09-04
| * Using $pos models for $bu0Clifford Wolf2014-09-03
| * Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-01
| * Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
| * Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
| * Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-16
| * Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16
| * Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
| * Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
| * Refactoring of CellType classClifford Wolf2014-08-14
| * Be more conservative with printing decimal numbers in verilog backendClifford Wolf2014-08-02
| * Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-02
| * No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
| * More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
| * Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
| * Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
| * Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-29
| * Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
| * Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
| * Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
| * Using log_assert() instead of assert()Clifford Wolf2014-07-28
| * Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
| * Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
| * Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
| * More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
| * Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
| * Manual fixes for new cell connections APIClifford Wolf2014-07-26
| * Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| * Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
| * Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
| * Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
| * Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
| * Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
| * Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
| * Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
| * SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
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