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* Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -paramClifford Wolf2014-02-21
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* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-12
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* disabling splice command in the scriptAhmed Irfan2014-02-11
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* register output correctedAhmed Irfan2014-02-11
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* added concat and slice cell translationAhmed Irfan2014-02-11
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* Added $slice and $concat cell typesClifford Wolf2014-02-07
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* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-06
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* Added BTOR backend README fileClifford Wolf2014-02-05
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* Added support for dump -appendClifford Wolf2014-02-04
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* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
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* Merge branch 'btor' of https://github.com/ahmedirfan1983/yosysClifford Wolf2014-01-26
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| * root bug correctedAhmed Irfan2014-01-25
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* | beautified write_intersynthJohann Glaser2014-01-25
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* removed regex includeAhmed Irfan2014-01-24
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* merged clifford changes + removed regexAhmed Irfan2014-01-24
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* Use techmap -share_map in btor scriptsClifford Wolf2014-01-24
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* Moved btor scripts to backends/btor/Clifford Wolf2014-01-24
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* slice bug correctedAhmed Irfan2014-01-20
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* assert featureAhmed Irfan2014-01-20
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* verilog default options pullAhmed Irfan2014-01-17
| | | | shift operator width issues
* slice error correctedAhmed Irfan2014-01-16
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* width issuesAhmed Irfan2014-01-15
| | | | dff cell for more than one registers
* BTOR backendAhmed Irfan2014-01-14
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* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-03
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| * Updated manual/command-reference-manual.texClifford Wolf2013-12-28
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| * Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
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* | btorAhmed Irfan2014-01-03
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
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* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
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* Fixed gentb_constant handling in autotest backendClifford Wolf2013-12-04
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* Added dump -m and -n optionsClifford Wolf2013-11-29
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* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-24
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* Added support for signed parameters in ilangClifford Wolf2013-11-24
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* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
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* Added modelsim support to autotestClifford Wolf2013-11-24
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* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-24
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* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
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* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-21
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* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
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* Silenced a gcc warning in spice backendClifford Wolf2013-11-09
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* Improved comments on topological sort in edif backendClifford Wolf2013-11-04
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* Added simple topological sort to edif backendClifford Wolf2013-11-03
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* Write yosys version to output filesClifford Wolf2013-11-03
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-11-03
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| * Ignore explicit unconnected ports in intersynth backendClifford Wolf2013-11-03
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* | Added placeholder check to dfflibmap and cleaned up some other placeholder ↵Clifford Wolf2013-10-31
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* Fixed hex string generation bug in edif backendClifford Wolf2013-10-27
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* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-24
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* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-24
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* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
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