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* Added yosys-smtbmc copyrightClifford Wolf2015-10-14
* Improvements in yosys-smtbmcClifford Wolf2015-10-14
* Added yosys-smtbmcClifford Wolf2015-10-14
* Implemented smtbmc.py -iClifford Wolf2015-10-14
* Added smtbmc.pyClifford Wolf2015-10-13
* Added write_smt2 -wiresClifford Wolf2015-10-13
* Bugfixes in writing of memories as VerilogClifford Wolf2015-09-25
* Added "yosys-smt2-wire" tag support to smt2 back-endClifford Wolf2015-08-31
* Fixed generation of smt2 concat statementsClifford Wolf2015-08-15
* Another block of spelling fixesLarry Doolittle2015-08-14
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-14
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-14
* Added "write_smt2 -regs"Clifford Wolf2015-08-12
* Added SMV back-end 'test_cells.sh' scriptClifford Wolf2015-08-12
* Use MEMID as name for $mem cellClifford Wolf2015-08-09
* Remove some very strange whitespace in btor.cc (by Larry Doolittle)Clifford Wolf2015-08-05
* Bugfix in SMV back-end for partially unassigned wiresClifford Wolf2015-08-05
* Added $assert support to SMV back-endClifford Wolf2015-08-04
* Improvements in BLIF back-endClifford Wolf2015-07-29
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added init support to SMV back-endClifford Wolf2015-06-19
* Progress in SMV back-endClifford Wolf2015-06-19
* Progress in SMV back-endClifford Wolf2015-06-19
* Progress in SMV back-endClifford Wolf2015-06-18
* Progress in SMV back-endClifford Wolf2015-06-17
* Progress in SMV back-endClifford Wolf2015-06-17
* Progress in SMV back-endClifford Wolf2015-06-16
* Progress in SMV back-endClifford Wolf2015-06-15
* Progress in SMV back-endClifford Wolf2015-06-15
* Added "write_smv" skeletonClifford Wolf2015-06-15
* Removed debug code from write_smt2Clifford Wolf2015-06-14
* Added write_smt2 -memClifford Wolf2015-06-14
* Fixed cstr_buf for std::string with small string optimizationClifford Wolf2015-06-11
* Improvements in cellaigs.cc and "json -aig"Clifford Wolf2015-06-11
* AigMaker refactoringClifford Wolf2015-06-10
* Added "json -aig"Clifford Wolf2015-06-10
* $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-08
* Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-04
* Improvements in BLIF front-endClifford Wolf2015-05-24
* Some fixes for $mem in verilog back-endClifford Wolf2015-05-20
* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-11
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| * Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-11
* | Disabled broken $mem support in verilog backendClifford Wolf2015-05-10
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* Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-10
* Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-08
* Added support for $mem cells in the verilog backend.luke whittlesey2015-05-07
* Minor fixes in handling of "init" attributeClifford Wolf2015-04-09
* Removed "techmap -share_map" (use "-map +/filename" instead)Clifford Wolf2015-04-08
* Added "port_directions" to write_json outputClifford Wolf2015-04-06
* Added "init" attribute support to verilog backendClifford Wolf2015-04-04
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