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* Sorting of object names in ilang backendClifford Wolf2014-09-19
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* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-06
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* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
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* Removed $bu0 cell typeClifford Wolf2014-09-04
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* Using $pos models for $bu0Clifford Wolf2014-09-03
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* Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵Clifford Wolf2014-09-01
| | | | RTLIL::SigChunk::data
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
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* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
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* Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-16
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* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-16
| | | | $_OAI4_
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
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* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
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* Refactoring of CellType classClifford Wolf2014-08-14
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* Be more conservative with printing decimal numbers in verilog backendClifford Wolf2014-08-02
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* Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-02
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* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
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* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-29
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* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
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* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
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* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
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* Manual fixes for new cell connections APIClifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
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* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
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* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-22
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-21
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* Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog ↵Clifford Wolf2014-07-20
| | | | backend
* Added support for $bu0 to verilog backendClifford Wolf2014-07-20
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* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
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* Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-07
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* Added $lut support to blif backend (by user eddiehung from reddit)Clifford Wolf2014-02-22
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* Better handling of nameDef and nameRef in edif backendClifford Wolf2014-02-21
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* Fixed instantiating multi-bit ports in edif backendClifford Wolf2014-02-21
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* Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -paramClifford Wolf2014-02-21
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