yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added support for dump -append	Clifford Wolf	2014-02-04
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
*	Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys	Clifford Wolf	2014-01-26
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\| *	root bug corrected	Ahmed Irfan	2014-01-25
* \|	beautified write_intersynth	Johann Glaser	2014-01-25
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*	removed regex include	Ahmed Irfan	2014-01-24
*	merged clifford changes + removed regex	Ahmed Irfan	2014-01-24
*	Use techmap -share_map in btor scripts	Clifford Wolf	2014-01-24
*	Moved btor scripts to backends/btor/	Clifford Wolf	2014-01-24
*	slice bug corrected	Ahmed Irfan	2014-01-20
*	assert feature	Ahmed Irfan	2014-01-20
*	verilog default options pull	Ahmed Irfan	2014-01-17
*	slice error corrected	Ahmed Irfan	2014-01-16
*	width issues	Ahmed Irfan	2014-01-15
*	BTOR backend	Ahmed Irfan	2014-01-14
*	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor	Ahmed Irfan	2014-01-03
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\| *	Updated manual/command-reference-manual.tex	Clifford Wolf	2013-12-28
\| *	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
* \|	btor	Ahmed Irfan	2014-01-03
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Fixed gentb_constant handling in autotest backend	Clifford Wolf	2013-12-04
*	Added dump -m and -n options	Clifford Wolf	2013-11-29
*	Added proper dumping of signed/unsigned parameters to verilog backend	Clifford Wolf	2013-11-24
*	Added support for signed parameters in ilang	Clifford Wolf	2013-11-24
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
*	Added modelsim support to autotest	Clifford Wolf	2013-11-24
*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
*	Implemented $_DFFSR_ expression generator in verilog backend	Clifford Wolf	2013-11-21
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
*	Silenced a gcc warning in spice backend	Clifford Wolf	2013-11-09
*	Improved comments on topological sort in edif backend	Clifford Wolf	2013-11-04
*	Added simple topological sort to edif backend	Clifford Wolf	2013-11-03
*	Write yosys version to output files	Clifford Wolf	2013-11-03
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-11-03
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\| *	Ignore explicit unconnected ports in intersynth backend	Clifford Wolf	2013-11-03
* \|	Added placeholder check to dfflibmap and cleaned up some other placeholder ch...	Clifford Wolf	2013-10-31
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*	Fixed hex string generation bug in edif backend	Clifford Wolf	2013-10-27
*	Added support for complex set-reset flip-flops in proc_dff	Clifford Wolf	2013-10-24
*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24
*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24
*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18
*	Added -buf, -true and -false options to blif backend	Clifford Wolf	2013-10-17
*	Improvements in EDIF backend	Clifford Wolf	2013-09-17
*	Added additional options to BLIF backend	Clifford Wolf	2013-09-15
*	Added BLIF backend	Clifford Wolf	2013-09-15
*	A couple of small fixes in SPICE backend	Clifford Wolf	2013-09-15
*	Added spice testbench to techlibs/cmos	Clifford Wolf	2013-09-14