yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Cosmetic changes in verilog output format	Clifford Wolf	2015-01-02
*	Fixed memory->start_offset handling	Clifford Wolf	2015-01-01
*	Replaced std::unordered_map as implementation for Yosys::dict	Clifford Wolf	2014-12-26
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26
*	Various fixes and improvements in "write_smt2 -bv"	Clifford Wolf	2014-12-25
*	Various fixes and improvements in write_smt2	Clifford Wolf	2014-12-25
*	Added support for most BV cell types to write_smt2	Clifford Wolf	2014-12-25
*	Added "write_smt2 -bv" and other write_smt2 improvements	Clifford Wolf	2014-12-25
*	Added write_smt2 (only gate level logic supported so far)	Clifford Wolf	2014-12-24
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24
*	Added $dffe support to write_verilog	Clifford Wolf	2014-12-20
*	Fixed another bug in write_blif handling of $lut cells	Clifford Wolf	2014-12-19
*	Fixed writing of $lut cells in BLIF backend	Clifford Wolf	2014-12-17
*	Added "write_blif -undef" and support for special "-" true/false/undef type	Clifford Wolf	2014-12-14
*	Added "write_blif -blackbox"	Clifford Wolf	2014-12-14
*	Added "blif -unbuf" feature	Clifford Wolf	2014-12-14
*	Added log_warning() API	Clifford Wolf	2014-11-09
*	Fixed generation of temp names in verilog backend	Clifford Wolf	2014-11-07
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor	Ahmed Irfan	2014-09-22
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\| *	Sorting of object names in ilang backend	Clifford Wolf	2014-09-19
\| *	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06
\| *	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
\| *	Removed $bu0 cell type	Clifford Wolf	2014-09-04
\| *	Using $pos models for $bu0	Clifford Wolf	2014-09-03
\| *	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01
\| *	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23
\| *	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23
\| *	Fixed AOI/OAI expr handling in verilog backend	Clifford Wolf	2014-08-16
\| *	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16
\| *	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15
\| *	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
\| *	Refactoring of CellType class	Clifford Wolf	2014-08-14
\| *	Be more conservative with printing decimal numbers in verilog backend	Clifford Wolf	2014-08-02
\| *	Improved verilog output for ordinary $mux cells	Clifford Wolf	2014-08-02
\| *	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
\| *	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
\| *	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
\| *	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
\| *	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29
\| *	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
\| *	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
\| *	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28
\| *	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
\| *	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
\| *	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
\| *	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
\| *	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26
\| *	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26