path: root/backends
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* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
* Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-07
* Added $lut support to blif backend (by user eddiehung from reddit)Clifford Wolf2014-02-22
* Better handling of nameDef and nameRef in edif backendClifford Wolf2014-02-21
* Fixed instantiating multi-bit ports in edif backendClifford Wolf2014-02-21
* Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -paramClifford Wolf2014-02-21
* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-12
* disabling splice command in the scriptAhmed Irfan2014-02-11
* register output correctedAhmed Irfan2014-02-11
* added concat and slice cell translationAhmed Irfan2014-02-11
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-06
* Added BTOR backend README fileClifford Wolf2014-02-05
* Added support for dump -appendClifford Wolf2014-02-04
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* Merge branch 'btor' of Wolf2014-01-26
| * root bug correctedAhmed Irfan2014-01-25
* | beautified write_intersynthJohann Glaser2014-01-25
* removed regex includeAhmed Irfan2014-01-24
* merged clifford changes + removed regexAhmed Irfan2014-01-24
* Use techmap -share_map in btor scriptsClifford Wolf2014-01-24
* Moved btor scripts to backends/btor/Clifford Wolf2014-01-24
* slice bug correctedAhmed Irfan2014-01-20
* assert featureAhmed Irfan2014-01-20
* verilog default options pullAhmed Irfan2014-01-17
* slice error correctedAhmed Irfan2014-01-16
* width issuesAhmed Irfan2014-01-15
* BTOR backendAhmed Irfan2014-01-14
* Merge branch 'master' of into btorAhmed Irfan2014-01-03
| * Updated manual/command-reference-manual.texClifford Wolf2013-12-28
| * Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* | btorAhmed Irfan2014-01-03
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Fixed gentb_constant handling in autotest backendClifford Wolf2013-12-04
* Added dump -m and -n optionsClifford Wolf2013-11-29
* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-24
* Added support for signed parameters in ilangClifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Added modelsim support to autotestClifford Wolf2013-11-24
* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-24
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-21
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Silenced a gcc warning in spice backendClifford Wolf2013-11-09
* Improved comments on topological sort in edif backendClifford Wolf2013-11-04
* Added simple topological sort to edif backendClifford Wolf2013-11-03
* Write yosys version to output filesClifford Wolf2013-11-03
* Merge branch 'master' of Wolf2013-11-03
| * Ignore explicit unconnected ports in intersynth backendClifford Wolf2013-11-03