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* Added "init" attribute support to verilog backendClifford Wolf2015-04-04
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* Update READMEAhmed Irfan2015-04-03
| | | corrected url
* Delete btor.ysAhmed Irfan2015-04-03
| | | .ys script not needed
* Update READMEAhmed Irfan2015-04-03
| | | pmux cell is implemented
* separated memory next from write cellAhmed Irfan2015-04-03
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* Added Verilog backend $dffsr supportClifford Wolf2015-03-18
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* Documentation for JSON format, added attributesClifford Wolf2015-03-06
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* Json bugfixClifford Wolf2015-03-03
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* Json backend improvementsClifford Wolf2015-03-03
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* Added write_blif -attrClifford Wolf2015-03-02
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* Added JSON backendClifford Wolf2015-03-02
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* Added $assume support to write_smt2Clifford Wolf2015-02-26
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* Minor "write_smt2" help msg changeClifford Wolf2015-02-22
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* Added "<mod>_a" and "<mod>_i" to write_smt2 outputClifford Wolf2015-02-22
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* Fixed "write_verilog -attr2comment" handling of "*/" in stringsClifford Wolf2015-02-13
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* Added EDIF backend support for multi-bit cell portsClifford Wolf2015-02-01
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* Shorter "dump" optionsClifford Wolf2015-01-31
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* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-24
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* Added dict/pool.sort()Clifford Wolf2015-01-24
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* Cosmetic changes in verilog output formatClifford Wolf2015-01-02
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* Fixed memory->start_offset handlingClifford Wolf2015-01-01
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* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-26
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
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* Various fixes and improvements in "write_smt2 -bv"Clifford Wolf2014-12-25
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* Various fixes and improvements in write_smt2Clifford Wolf2014-12-25
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* Added support for most BV cell types to write_smt2Clifford Wolf2014-12-25
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* Added "write_smt2 -bv" and other write_smt2 improvementsClifford Wolf2014-12-25
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* Added write_smt2 (only gate level logic supported so far)Clifford Wolf2014-12-24
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* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-24
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* Added $dffe support to write_verilogClifford Wolf2014-12-20
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* Fixed another bug in write_blif handling of $lut cellsClifford Wolf2014-12-19
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* Fixed writing of $lut cells in BLIF backendClifford Wolf2014-12-17
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* Added "write_blif -undef" and support for special "-" true/false/undef typeClifford Wolf2014-12-14
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* Added "write_blif -blackbox"Clifford Wolf2014-12-14
| | | | | based on code by Eddie Hung from https://github.com/eddiehung/yosys/commit/1e481661cb4a4
* Added "blif -unbuf" featureClifford Wolf2014-12-14
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* Added log_warning() APIClifford Wolf2014-11-09
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* Fixed generation of temp names in verilog backendClifford Wolf2014-11-07
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
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* namespace YosysClifford Wolf2014-09-27
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* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-09-22
|\ | | | | | | | | | | | | | | | | added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc
| * Sorting of object names in ilang backendClifford Wolf2014-09-19
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| * Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-06
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| * Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
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| * Removed $bu0 cell typeClifford Wolf2014-09-04
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| * Using $pos models for $bu0Clifford Wolf2014-09-03
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| * Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵Clifford Wolf2014-09-01
| | | | | | | | RTLIL::SigChunk::data
| * Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
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| * Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
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| * Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-16
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| * Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-16
| | | | | | | | $_OAI4_
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