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* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-18
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* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
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* Added -buf, -true and -false options to blif backendClifford Wolf2013-10-17
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* Improvements in EDIF backendClifford Wolf2013-09-17
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* Added additional options to BLIF backendClifford Wolf2013-09-15
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* Added BLIF backendClifford Wolf2013-09-15
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* A couple of small fixes in SPICE backendClifford Wolf2013-09-15
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* Added spice testbench to techlibs/cmosClifford Wolf2013-09-14
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* Added spice backendClifford Wolf2013-09-14
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-09-03
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| * Encode large (>32 bits) parameters as hex string in edif backendClifford Wolf2013-08-28
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| * Improved edif backendClifford Wolf2013-08-27
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* | Added -selected option to various backendsClifford Wolf2013-09-03
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* More explicit integer output in verilog backendClifford Wolf2013-08-22
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* Added correct encoding of identifiers in EDIF backendClifford Wolf2013-08-22
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* Added edif backend (still under construction)Clifford Wolf2013-08-22
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* Fixed generation of newlines in "dump" outputClifford Wolf2013-06-10
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* Added "dump" command (part ilang backend)Clifford Wolf2013-06-02
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* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
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* Added -notypes option to intersynth backendClifford Wolf2013-03-24
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* Fixed gcc build (intersynth backend)Clifford Wolf2013-03-23
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* Various improvements in intersynth backendClifford Wolf2013-03-23
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* Added intersynth backendClifford Wolf2013-03-23
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* Avoid verilog-2k in verilog backendClifford Wolf2013-03-21
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* More support code for $sr cellsClifford Wolf2013-03-14
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* Fixed a gcc compiler warning [-Wparentheses]Clifford Wolf2013-03-03
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* Added more help messagesClifford Wolf2013-03-01
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* initial importClifford Wolf2013-01-05