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| * Manual fixes for new cell connections APIClifford Wolf2014-07-26
| * Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| * Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
| * Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
| * Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
| * Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
| * Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
| * Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
| * Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
| * SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
| * SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
| * SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
| * Added "autoidx" statement to ilang file formatClifford Wolf2014-07-21
| * Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...Clifford Wolf2014-07-20
| * Added support for $bu0 to verilog backendClifford Wolf2014-07-20
| * Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
| * Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-07
| * Added $lut support to blif backend (by user eddiehung from reddit)Clifford Wolf2014-02-22
| * Better handling of nameDef and nameRef in edif backendClifford Wolf2014-02-21
| * Fixed instantiating multi-bit ports in edif backendClifford Wolf2014-02-21
| * Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -paramClifford Wolf2014-02-21
* | fixed memory next issue, when same memory is written in different case statementahmedirfan19832014-09-18
* | added $pmux cell translationAhmed Irfan2014-09-02
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* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-12
* disabling splice command in the scriptAhmed Irfan2014-02-11
* register output correctedAhmed Irfan2014-02-11
* added concat and slice cell translationAhmed Irfan2014-02-11
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-06
* Added BTOR backend README fileClifford Wolf2014-02-05
* Added support for dump -appendClifford Wolf2014-02-04
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* Merge branch 'btor' of https://github.com/ahmedirfan1983/yosysClifford Wolf2014-01-26
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| * root bug correctedAhmed Irfan2014-01-25
* | beautified write_intersynthJohann Glaser2014-01-25
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* removed regex includeAhmed Irfan2014-01-24
* merged clifford changes + removed regexAhmed Irfan2014-01-24
* Use techmap -share_map in btor scriptsClifford Wolf2014-01-24
* Moved btor scripts to backends/btor/Clifford Wolf2014-01-24
* slice bug correctedAhmed Irfan2014-01-20
* assert featureAhmed Irfan2014-01-20
* verilog default options pullAhmed Irfan2014-01-17
* slice error correctedAhmed Irfan2014-01-16
* width issuesAhmed Irfan2014-01-15
* BTOR backendAhmed Irfan2014-01-14
* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-03
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| * Updated manual/command-reference-manual.texClifford Wolf2013-12-28
| * Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* | btorAhmed Irfan2014-01-03
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04