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* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* Refactoring of CellType classClifford Wolf2014-08-14
* Be more conservative with printing decimal numbers in verilog backendClifford Wolf2014-08-02
* Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-02
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-29
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-21
* Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...Clifford Wolf2014-07-20
* Added support for $bu0 to verilog backendClifford Wolf2014-07-20
* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
* Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-07
* Added $lut support to blif backend (by user eddiehung from reddit)Clifford Wolf2014-02-22
* Better handling of nameDef and nameRef in edif backendClifford Wolf2014-02-21
* Fixed instantiating multi-bit ports in edif backendClifford Wolf2014-02-21
* Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -paramClifford Wolf2014-02-21
* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-12
* disabling splice command in the scriptAhmed Irfan2014-02-11
* register output correctedAhmed Irfan2014-02-11
* added concat and slice cell translationAhmed Irfan2014-02-11
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-06
* Added BTOR backend README fileClifford Wolf2014-02-05
* Added support for dump -appendClifford Wolf2014-02-04
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* Merge branch 'btor' of https://github.com/ahmedirfan1983/yosysClifford Wolf2014-01-26
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| * root bug correctedAhmed Irfan2014-01-25