yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Added "autoidx" statement to ilang file format	Clifford Wolf	2014-07-21
*	Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...	Clifford Wolf	2014-07-20
*	Added support for $bu0 to verilog backend	Clifford Wolf	2014-07-20
*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13
*	Use log_abort() and log_assert() in BTOR backend	Clifford Wolf	2014-03-07
*	Added $lut support to blif backend (by user eddiehung from reddit)	Clifford Wolf	2014-02-22
*	Better handling of nameDef and nameRef in edif backend	Clifford Wolf	2014-02-21
*	Fixed instantiating multi-bit ports in edif backend	Clifford Wolf	2014-02-21
*	Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param	Clifford Wolf	2014-02-21
*	modified btor synthesis script for correct use of splice command.	Ahmed Irfan	2014-02-12
*	disabling splice command in the script	Ahmed Irfan	2014-02-11
*	register output corrected	Ahmed Irfan	2014-02-11
*	added concat and slice cell translation	Ahmed Irfan	2014-02-11
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07
*	Fixed gcc compiler warnings with release build	Clifford Wolf	2014-02-06
*	Added BTOR backend README file	Clifford Wolf	2014-02-05
*	Added support for dump -append	Clifford Wolf	2014-02-04
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
*	Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys	Clifford Wolf	2014-01-26
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\| *	root bug corrected	Ahmed Irfan	2014-01-25
* \|	beautified write_intersynth	Johann Glaser	2014-01-25
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*	removed regex include	Ahmed Irfan	2014-01-24
*	merged clifford changes + removed regex	Ahmed Irfan	2014-01-24
*	Use techmap -share_map in btor scripts	Clifford Wolf	2014-01-24
*	Moved btor scripts to backends/btor/	Clifford Wolf	2014-01-24
*	slice bug corrected	Ahmed Irfan	2014-01-20
*	assert feature	Ahmed Irfan	2014-01-20
*	verilog default options pull	Ahmed Irfan	2014-01-17
*	slice error corrected	Ahmed Irfan	2014-01-16
*	width issues	Ahmed Irfan	2014-01-15
*	BTOR backend	Ahmed Irfan	2014-01-14
*	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor	Ahmed Irfan	2014-01-03
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\| *	Updated manual/command-reference-manual.tex	Clifford Wolf	2013-12-28
\| *	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
* \|	btor	Ahmed Irfan	2014-01-03
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