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* Improvements in cellaigs.cc and "json -aig"Clifford Wolf2015-06-11
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* AigMaker refactoringClifford Wolf2015-06-10
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* Added "json -aig"Clifford Wolf2015-06-10
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* $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-08
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* Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-04
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* Improvements in BLIF front-endClifford Wolf2015-05-24
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* Some fixes for $mem in verilog back-endClifford Wolf2015-05-20
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* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-11
|\ | | | | Fixed bug in $mem cell verilog code generation.
| * Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-11
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* | Disabled broken $mem support in verilog backendClifford Wolf2015-05-10
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* Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-10
| | | | | | Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used dict<> instead of std::map, and used RTLIL::SigSpec instead of std::vector.
* Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-08
| | | | write-enable bits and RD_TRANSPARENT parameter settings.
* Added support for $mem cells in the verilog backend.luke whittlesey2015-05-07
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* Minor fixes in handling of "init" attributeClifford Wolf2015-04-09
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* Removed "techmap -share_map" (use "-map +/filename" instead)Clifford Wolf2015-04-08
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* Added "port_directions" to write_json outputClifford Wolf2015-04-06
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* Added "init" attribute support to verilog backendClifford Wolf2015-04-04
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* Update READMEAhmed Irfan2015-04-03
| | | corrected url
* Delete btor.ysAhmed Irfan2015-04-03
| | | .ys script not needed
* Update READMEAhmed Irfan2015-04-03
| | | pmux cell is implemented
* separated memory next from write cellAhmed Irfan2015-04-03
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* Added Verilog backend $dffsr supportClifford Wolf2015-03-18
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* Documentation for JSON format, added attributesClifford Wolf2015-03-06
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* Json bugfixClifford Wolf2015-03-03
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* Json backend improvementsClifford Wolf2015-03-03
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* Added write_blif -attrClifford Wolf2015-03-02
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* Added JSON backendClifford Wolf2015-03-02
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* Added $assume support to write_smt2Clifford Wolf2015-02-26
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* Minor "write_smt2" help msg changeClifford Wolf2015-02-22
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* Added "<mod>_a" and "<mod>_i" to write_smt2 outputClifford Wolf2015-02-22
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* Fixed "write_verilog -attr2comment" handling of "*/" in stringsClifford Wolf2015-02-13
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* Added EDIF backend support for multi-bit cell portsClifford Wolf2015-02-01
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* Shorter "dump" optionsClifford Wolf2015-01-31
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* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-24
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* Added dict/pool.sort()Clifford Wolf2015-01-24
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* Cosmetic changes in verilog output formatClifford Wolf2015-01-02
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* Fixed memory->start_offset handlingClifford Wolf2015-01-01
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* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-26
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
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* Various fixes and improvements in "write_smt2 -bv"Clifford Wolf2014-12-25
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* Various fixes and improvements in write_smt2Clifford Wolf2014-12-25
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* Added support for most BV cell types to write_smt2Clifford Wolf2014-12-25
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* Added "write_smt2 -bv" and other write_smt2 improvementsClifford Wolf2014-12-25
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* Added write_smt2 (only gate level logic supported so far)Clifford Wolf2014-12-24
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* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-24
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* Added $dffe support to write_verilogClifford Wolf2014-12-20
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* Fixed another bug in write_blif handling of $lut cellsClifford Wolf2014-12-19
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* Fixed writing of $lut cells in BLIF backendClifford Wolf2014-12-17
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* Added "write_blif -undef" and support for special "-" true/false/undef typeClifford Wolf2014-12-14
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* Added "write_blif -blackbox"Clifford Wolf2014-12-14
| | | | | based on code by Eddie Hung from https://github.com/eddiehung/yosys/commit/1e481661cb4a4
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