path: root/frontends/ast/
Commit message (Expand)AuthorAge
* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-19
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-27
* Fixed AST_CONSTANT node generationClifford Wolf2013-07-07
* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-10
* Added log_assert() apiClifford Wolf2013-05-24
* Fixed handling of positional module parametersClifford Wolf2013-04-26
* Only use sha1 checksums for names of parametric modules when the verbose form...Clifford Wolf2013-04-26
* Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-31
* Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
* Added mem2reg option to verilog frontendClifford Wolf2013-03-24
* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-27
* Added support for verilog genblock[index].member syntaxClifford Wolf2013-02-26
* initial importClifford Wolf2013-01-05