yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20
*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
*	Added dumping of attributes in AST frontend	Clifford Wolf	2013-11-18
*	Call internal checker more often	Clifford Wolf	2013-11-10
*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07
*	Various ast changes for early expression width detection (prep for constfold ...	Clifford Wolf	2013-11-02
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24
*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19
*	Added "design" command (-reset, -save, -load)	Clifford Wolf	2013-07-27
*	Fixed AST_CONSTANT node generation	Clifford Wolf	2013-07-07
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10
*	Added log_assert() api	Clifford Wolf	2013-05-24
*	Fixed handling of positional module parameters	Clifford Wolf	2013-04-26
*	Only use sha1 checksums for names of parametric modules when the verbose form...	Clifford Wolf	2013-04-26
*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31
*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27
*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26
*	initial import	Clifford Wolf	2013-01-05