yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	Clifford Wolf	2014-06-16
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*	Improved AstNode::realAsConst for large numbers	Clifford Wolf	2014-06-15
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*	Improved AstNode::asReal for large integers	Clifford Wolf	2014-06-15
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*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14
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*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14
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*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14
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*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13
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*	Add support for cell arrays	Clifford Wolf	2014-06-07
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*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06
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*	Include id2ast pointers when dumping AST	Clifford Wolf	2014-03-05
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*	Cleanups in handling of read_verilog -defer and -icells	Clifford Wolf	2014-02-20
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*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17
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*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14
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*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14
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*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13
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*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01
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*	Added read_verilog -icells option	Clifford Wolf	2014-01-29
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*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20
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*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19
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*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
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*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05
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*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05
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*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
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*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24
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*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
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*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
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*	Added dumping of attributes in AST frontend	Clifford Wolf	2013-11-18
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*	Call internal checker more often	Clifford Wolf	2013-11-10
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*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07
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*	Various ast changes for early expression width detection (prep for constfold ↵	Clifford Wolf	2013-11-02
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*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24
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*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19
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*	Added "design" command (-reset, -save, -load)	Clifford Wolf	2013-07-27
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*	Fixed AST_CONSTANT node generation	Clifford Wolf	2013-07-07
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*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04
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*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10
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*	Added log_assert() api	Clifford Wolf	2013-05-24
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*	Fixed handling of positional module parameters	Clifford Wolf	2013-04-26
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*	Only use sha1 checksums for names of parametric modules when the verbose ↵	Clifford Wolf	2013-04-26
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*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31
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*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31
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*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28
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*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24
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*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27
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*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26
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*	initial import	Clifford Wolf	2013-01-05