yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22
*	Added AstNode::asInt()	Clifford Wolf	2014-08-21
*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21
*	Added support for global tasks and functions	Clifford Wolf	2014-08-21
*	Added const folding of AST_CASE to AST simplifier	Clifford Wolf	2014-08-18
*	Use stackmap<> in AST ProcessGenerator	Clifford Wolf	2014-08-17
*	Fixed bug in "read_verilog -ignore_redef"	Clifford Wolf	2014-08-15
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14
*	Added module->ports	Clifford Wolf	2014-08-14
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	Clifford Wolf	2014-06-16
*	Improved AstNode::realAsConst for large numbers	Clifford Wolf	2014-06-15
*	Improved AstNode::asReal for large integers	Clifford Wolf	2014-06-15
*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14
*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14
*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14
*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13
*	Add support for cell arrays	Clifford Wolf	2014-06-07
*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06
*	Include id2ast pointers when dumping AST	Clifford Wolf	2014-03-05
*	Cleanups in handling of read_verilog -defer and -icells	Clifford Wolf	2014-02-20
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17
*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29
*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20
*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
*	Added dumping of attributes in AST frontend	Clifford Wolf	2013-11-18
*	Call internal checker more often	Clifford Wolf	2013-11-10
*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07