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* Added AstNode::asInt()Clifford Wolf2014-08-21
* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-21
* Added support for global tasks and functionsClifford Wolf2014-08-21
* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-18
* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-17
* Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-15
* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-14
* Added module->portsClifford Wolf2014-08-14
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-06
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-02
* Replaced sha1 implementationClifford Wolf2014-08-01
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added proper Design->addModule interfaceClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012Clifford Wolf2014-06-16
* Improved AstNode::realAsConst for large numbersClifford Wolf2014-06-15
* Improved AstNode::asReal for large integersClifford Wolf2014-06-15
* improved (fixed) conversion of real values to bit vectorsClifford Wolf2014-06-14
* Added handling of real-valued parameters/localparamsClifford Wolf2014-06-14
* Implemented basic real arithmeticClifford Wolf2014-06-14
* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-13
* Add support for cell arraysClifford Wolf2014-06-07
* added while and repeat support to verilog parserClifford Wolf2014-06-06
* Include id2ast pointers when dumping ASTClifford Wolf2014-03-05
* Cleanups in handling of read_verilog -defer and -icellsClifford Wolf2014-02-20
* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-17
* Added support for FOR loops in function calls in parametersClifford Wolf2014-02-14
* Created basic support for function calls in parameter valuesClifford Wolf2014-02-14
* Implemented read_verilog -deferClifford Wolf2014-02-13
* Added constant size expression support of sized constantsClifford Wolf2014-02-01
* Added read_verilog -icells optionClifford Wolf2014-01-29
* Fixed algorithmic complexity of AST simplification of long expressionsClifford Wolf2014-01-20
* Added Verilog parser support for assertsClifford Wolf2014-01-19
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Keep strings as strings in const ternary and concatClifford Wolf2013-12-05
* Added AstNode::mkconst_str APIClifford Wolf2013-12-05
* Various improvements in support for generate statementsClifford Wolf2013-12-04
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Added dumping of attributes in AST frontendClifford Wolf2013-11-18
* Call internal checker more oftenClifford Wolf2013-11-10
* Various fixes for correct parameter supportClifford Wolf2013-11-07
* Various ast changes for early expression width detection (prep for constfold ...Clifford Wolf2013-11-02