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Author
Age
*
Added dumping of attributes in AST frontend
Clifford Wolf
2013-11-18
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Call internal checker more often
Clifford Wolf
2013-11-10
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Various fixes for correct parameter support
Clifford Wolf
2013-11-07
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Various ast changes for early expression width detection (prep for constfold ...
Clifford Wolf
2013-11-02
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Fixed handling of boolean attributes (frontends)
Clifford Wolf
2013-10-24
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Improved ast dumping (ast/verilog frontend)
Clifford Wolf
2013-08-19
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Added "design" command (-reset, -save, -load)
Clifford Wolf
2013-07-27
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Fixed AST_CONSTANT node generation
Clifford Wolf
2013-07-07
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Added defparam support to Verilog/AST frontend
Clifford Wolf
2013-07-04
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Enabled AST/Verilog front-end optimizations per default
Clifford Wolf
2013-06-10
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Added log_assert() api
Clifford Wolf
2013-05-24
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Fixed handling of positional module parameters
Clifford Wolf
2013-04-26
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Only use sha1 checksums for names of parametric modules when the verbose form...
Clifford Wolf
2013-04-26
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Now only use value from "initial" when no matching "always" block is found
Clifford Wolf
2013-03-31
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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
Clifford Wolf
2013-03-31
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Implemented proper handling of stub placeholder modules
Clifford Wolf
2013-03-28
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Added mem2reg option to verilog frontend
Clifford Wolf
2013-03-24
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Moved stand-alone libs to libs/ directory and added libs/subcircuit
Clifford Wolf
2013-02-27
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Added support for verilog genblock[index].member syntax
Clifford Wolf
2013-02-26
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initial import
Clifford Wolf
2013-01-05