yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Imported yosys 0.7	Ruben Undheim	2016-11-03
*	Squashed commit of the following:	Ruben Undheim	2016-09-23
*	Fixed some visual studio warnings	Clifford Wolf	2016-02-13
*	Fixed segfault in AstNode::asReal	Clifford Wolf	2015-09-25
*	Fixed AstNode::mkconst_bits() segfault on zero-sized constant	Clifford Wolf	2015-09-24
*	Another block of spelling fixes	Larry Doolittle	2015-08-14
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26
*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14
*	Creating $meminit cells in verilog front-end	Clifford Wolf	2015-02-14
*	Added global yosys_celltypes	Clifford Wolf	2014-12-29
*	dict/pool changes in ast	Clifford Wolf	2014-12-29
*	Changed more code to dict<> and pool<>	Clifford Wolf	2014-12-28
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26
*	Fixed constant "cond ? string1 : string2" with strings of different size	Clifford Wolf	2014-10-25
*	minor indenting corrections	Clifford Wolf	2014-10-19
*	Builds on Mac 10.9.2 with LLVM 3.5.	Parviz Palangpour	2014-10-19
*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22
*	Added AstNode::asInt()	Clifford Wolf	2014-08-21
*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21
*	Added support for global tasks and functions	Clifford Wolf	2014-08-21
*	Added const folding of AST_CASE to AST simplifier	Clifford Wolf	2014-08-18
*	Use stackmap<> in AST ProcessGenerator	Clifford Wolf	2014-08-17
*	Fixed bug in "read_verilog -ignore_redef"	Clifford Wolf	2014-08-15
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14
*	Added module->ports	Clifford Wolf	2014-08-14
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	Clifford Wolf	2014-06-16
*	Improved AstNode::realAsConst for large numbers	Clifford Wolf	2014-06-15
*	Improved AstNode::asReal for large integers	Clifford Wolf	2014-06-15
*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14
*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14
*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14
*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13
*	Add support for cell arrays	Clifford Wolf	2014-06-07
*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06
*	Include id2ast pointers when dumping AST	Clifford Wolf	2014-03-05
*	Cleanups in handling of read_verilog -defer and -icells	Clifford Wolf	2014-02-20
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17
*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14