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path: root/frontends/ast/ast.h
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* New upstream version 0.9Ruben Undheim2019-10-18
* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Squashed commit of the following:Ruben Undheim2016-09-23
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-14
* Added WORDS parameter to $meminitClifford Wolf2015-07-31
* Fixed nested mem2regClifford Wolf2015-07-29
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added non-std verilog assume() statementClifford Wolf2015-02-26
* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-14
* Creating $meminit cells in verilog front-endClifford Wolf2015-02-14
* dict/pool changes in astClifford Wolf2014-12-29
* Changed more code to dict<> and pool<>Clifford Wolf2014-12-28
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
* Added support for $readmemh/$readmembClifford Wolf2014-10-26
* Fixed handling of invalid array access in mem2reg codeClifford Wolf2014-10-16
* Added AstNode::asInt()Clifford Wolf2014-08-21
* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-21
* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-18
* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-17
* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-14
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-06
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-05
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
* Added AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-17
* Added found_real feature to AstNode::detectSignWidthClifford Wolf2014-06-16
* improved (fixed) conversion of real values to bit vectorsClifford Wolf2014-06-14
* Implemented basic real arithmeticClifford Wolf2014-06-14
* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-13
* Add support for cell arraysClifford Wolf2014-06-07
* further improved const function supportClifford Wolf2014-06-07
* improved const function supportClifford Wolf2014-06-06
* added while and repeat support to verilog parserClifford Wolf2014-06-06
* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-17
* Added support for FOR loops in function calls in parametersClifford Wolf2014-02-14
* Created basic support for function calls in parameter valuesClifford Wolf2014-02-14
* Implemented read_verilog -deferClifford Wolf2014-02-13
* Added constant size expression support of sized constantsClifford Wolf2014-02-01
* Added read_verilog -icells optionClifford Wolf2014-01-29
* Fixed algorithmic complexity of AST simplification of long expressionsClifford Wolf2014-01-20
* Added Verilog parser support for assertsClifford Wolf2014-01-19
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Keep strings as strings in const ternary and concatClifford Wolf2013-12-05
* Added AstNode::mkconst_str APIClifford Wolf2013-12-05
* Various improvements in support for generate statementsClifford Wolf2013-12-04
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24