yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14
*	Added WORDS parameter to $meminit	Clifford Wolf	2015-07-31
*	Fixed nested mem2reg	Clifford Wolf	2015-07-29
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26
*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14
*	Creating $meminit cells in verilog front-end	Clifford Wolf	2015-02-14
*	dict/pool changes in ast	Clifford Wolf	2014-12-29
*	Changed more code to dict<> and pool<>	Clifford Wolf	2014-12-28
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26
*	Added support for $readmemh/$readmemb	Clifford Wolf	2014-10-26
*	Fixed handling of invalid array access in mem2reg code	Clifford Wolf	2014-10-16
*	Added AstNode::asInt()	Clifford Wolf	2014-08-21
*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21
*	Added const folding of AST_CASE to AST simplifier	Clifford Wolf	2014-08-18
*	Use stackmap<> in AST ProcessGenerator	Clifford Wolf	2014-08-17
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06
*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
*	Added AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17
*	Added found_real feature to AstNode::detectSignWidth	Clifford Wolf	2014-06-16
*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14
*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14
*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13
*	Add support for cell arrays	Clifford Wolf	2014-06-07
*	further improved const function support	Clifford Wolf	2014-06-07
*	improved const function support	Clifford Wolf	2014-06-06
*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17
*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29
*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20
*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
*	Various ast changes for early expression width detection (prep for constfold ...	Clifford Wolf	2013-11-02
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24