yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added found_real feature to AstNode::detectSignWidth	Clifford Wolf	2014-06-16
*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14
*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14
*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13
*	Add support for cell arrays	Clifford Wolf	2014-06-07
*	further improved const function support	Clifford Wolf	2014-06-07
*	improved const function support	Clifford Wolf	2014-06-06
*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17
*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29
*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20
*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
*	Various ast changes for early expression width detection (prep for constfold ...	Clifford Wolf	2013-11-02
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24
*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19
*	Added "design" command (-reset, -save, -load)	Clifford Wolf	2013-07-27
*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10
*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31
*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28
*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24
*	Improved mem2reg handling in ast simplifier	Clifford Wolf	2013-03-24
*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26
*	initial import	Clifford Wolf	2013-01-05