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path: root/frontends/ast/ast.h
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* Added found_real feature to AstNode::detectSignWidthClifford Wolf2014-06-16
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* improved (fixed) conversion of real values to bit vectorsClifford Wolf2014-06-14
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* Implemented basic real arithmeticClifford Wolf2014-06-14
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* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-13
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* Add support for cell arraysClifford Wolf2014-06-07
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* further improved const function supportClifford Wolf2014-06-07
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* improved const function supportClifford Wolf2014-06-06
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* added while and repeat support to verilog parserClifford Wolf2014-06-06
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* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-17
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* Added support for FOR loops in function calls in parametersClifford Wolf2014-02-14
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* Created basic support for function calls in parameter valuesClifford Wolf2014-02-14
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* Implemented read_verilog -deferClifford Wolf2014-02-13
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* Added constant size expression support of sized constantsClifford Wolf2014-02-01
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* Added read_verilog -icells optionClifford Wolf2014-01-29
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* Fixed algorithmic complexity of AST simplification of long expressionsClifford Wolf2014-01-20
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* Added Verilog parser support for assertsClifford Wolf2014-01-19
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* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
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* Keep strings as strings in const ternary and concatClifford Wolf2013-12-05
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* Added AstNode::mkconst_str APIClifford Wolf2013-12-05
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* Various improvements in support for generate statementsClifford Wolf2013-12-04
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
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* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
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* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
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* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
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* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
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* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
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* Various ast changes for early expression width detection (prep for constfold ↵Clifford Wolf2013-11-02
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* Fixed handling of boolean attributes (frontends)Clifford Wolf2013-10-24
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* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-19
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* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-27
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* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
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* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
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* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-10
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* Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-31
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* Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
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* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
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* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-25
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* Added mem2reg option to verilog frontendClifford Wolf2013-03-24
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* Improved mem2reg handling in ast simplifierClifford Wolf2013-03-24
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* Added support for verilog genblock[index].member syntaxClifford Wolf2013-02-26
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* initial importClifford Wolf2013-01-05