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path: root/frontends/ast/ast.h
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* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-17
* Added support for FOR loops in function calls in parametersClifford Wolf2014-02-14
* Created basic support for function calls in parameter valuesClifford Wolf2014-02-14
* Implemented read_verilog -deferClifford Wolf2014-02-13
* Added constant size expression support of sized constantsClifford Wolf2014-02-01
* Added read_verilog -icells optionClifford Wolf2014-01-29
* Fixed algorithmic complexity of AST simplification of long expressionsClifford Wolf2014-01-20
* Added Verilog parser support for assertsClifford Wolf2014-01-19
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Keep strings as strings in const ternary and concatClifford Wolf2013-12-05
* Added AstNode::mkconst_str APIClifford Wolf2013-12-05
* Various improvements in support for generate statementsClifford Wolf2013-12-04
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Various ast changes for early expression width detection (prep for constfold ...Clifford Wolf2013-11-02
* Fixed handling of boolean attributes (frontends)Clifford Wolf2013-10-24
* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-19
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-27
* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-10
* Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-31
* Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-25
* Added mem2reg option to verilog frontendClifford Wolf2013-03-24
* Improved mem2reg handling in ast simplifierClifford Wolf2013-03-24
* Added support for verilog genblock[index].member syntaxClifford Wolf2013-02-26
* initial importClifford Wolf2013-01-05