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path: root/frontends/ast/genrtlil.cc
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* Added $assert cellClifford Wolf2014-01-19
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* Added correct handling of $memwr priorityClifford Wolf2014-01-03
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* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
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* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
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* Various improvements in support for generate statementsClifford Wolf2013-12-04
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
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* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
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* Added support for local regs in named blocksClifford Wolf2013-12-04
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* Fixed temp net name generation in rtlil process generator for abbreviated ↵Clifford Wolf2013-11-28
| | | | name matching
* Added "src" attribute to processesClifford Wolf2013-11-28
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* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-24
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* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
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* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
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* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
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* Fixed parsing of default cases when not last caseClifford Wolf2013-11-18
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* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
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* More undef-propagation related fixesClifford Wolf2013-11-08
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* Fixed handling of power operatorClifford Wolf2013-11-07
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* Fixed more extend vs. extend_u0 issuesClifford Wolf2013-11-07
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* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-07
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* Fixed const folding in corner cases with parametersClifford Wolf2013-11-07
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* Fixed width detection for replicate operatorClifford Wolf2013-11-07
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* Various fixes for correct parameter supportClifford Wolf2013-11-07
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* Fixed the fix for propagation of width hints for $signed() and $unsigned()Clifford Wolf2013-11-07
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* Fixed propagation of width hints for $signed() and $unsigned()Clifford Wolf2013-11-06
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* Additional fixes for undef propagation in concat and replicate opsClifford Wolf2013-11-06
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* Improved width extension with regard to undef propagationClifford Wolf2013-11-06
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* further improved early width and sign detection in ast simplifierClifford Wolf2013-11-04
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* Fixed detectSignWidthWorker (ast frontend) for AST_CONCATClifford Wolf2013-11-03
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* Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing ↵Clifford Wolf2013-11-02
| | | | before constfold fixes)
* Various ast changes for early expression width detection (prep for constfold ↵Clifford Wolf2013-11-02
| | | | fixes)
* Fixed handling of boolean attributes (frontends)Clifford Wolf2013-10-24
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* Fixed width and sign detection for ** operatorClifford Wolf2013-08-19
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* Added support for "2**n" shifter encodingClifford Wolf2013-08-12
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* Added $div and $mod technology mappingClifford Wolf2013-08-09
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* More fixes in ternary op sign handlingClifford Wolf2013-07-12
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* Fixed sign handling in ternary operatorClifford Wolf2013-07-12
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* Another vloghammer related bugfixClifford Wolf2013-07-11
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* Fixed sign propagation in bit-wise operatorsClifford Wolf2013-07-09
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* More fixes in ast expression sign/width handlingClifford Wolf2013-07-09
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* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
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* Fixed another bug found using vloghammerClifford Wolf2013-07-07
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* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
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* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
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* Sign-extension related fixes in SatGen and AST frontendClifford Wolf2013-06-10
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* Fixes and improvements in AST const foldingClifford Wolf2013-06-10
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* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-10
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* Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵Clifford Wolf2013-04-13
| | | | as case values
* Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-31
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* Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
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