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genrtlil.cc
Commit message (
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Author
Age
*
Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
*
Fixed assignment of out-of bounds array element
Clifford Wolf
2014-09-06
*
Removed $bu0 cell type
Clifford Wolf
2014-09-04
*
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
Clifford Wolf
2014-08-21
*
Improved AST ProcessGenerator performance
Clifford Wolf
2014-08-17
*
Use stackmap<> in AST ProcessGenerator
Clifford Wolf
2014-08-17
*
AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
Clifford Wolf
2014-08-16
*
Added RTLIL::SigSpec::to_sigbit_map()
Clifford Wolf
2014-08-14
*
Changed the AST genWidthRTLIL subst interface to use a std::map
Clifford Wolf
2014-08-14
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
*
Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
*
Removed left over debug code
Clifford Wolf
2014-07-28
*
Fixed part selects of parameters
Clifford Wolf
2014-07-28
*
Set results of out-of-bounds static bit/part select to undef
Clifford Wolf
2014-07-28
*
Fixed RTLIL code generator for part select of parameter
Clifford Wolf
2014-07-28
*
Fixed width detection for part selects
Clifford Wolf
2014-07-28
*
Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
*
Added wire->upto flag for signals such as "wire [0:7] x;"
Clifford Wolf
2014-07-28
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Fixed signdness detection of expressions with bit- and part-selects
Clifford Wolf
2014-07-28
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Replaced more old SigChunk programming patterns
Clifford Wolf
2014-07-24
*
Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
*
SigSpec refactoring: More cleanups of old SigSpec use pattern
Clifford Wolf
2014-07-22
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
*
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
Clifford Wolf
2014-07-22
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
changes in verilog frontend for new $mem/$memwr WR_EN interface
Clifford Wolf
2014-07-16
*
More found_real-related fixes to AstNode::detectSignWidthWorker
Clifford Wolf
2014-06-24
*
fixed signdness detection for expressions with reals
Clifford Wolf
2014-06-21
*
Added found_real feature to AstNode::detectSignWidth
Clifford Wolf
2014-06-16
*
improved (fixed) conversion of real values to bit vectors
Clifford Wolf
2014-06-14
*
Added real->int convertion in ast genrtlil
Clifford Wolf
2014-06-14
*
further improved const function support
Clifford Wolf
2014-06-07
*
improved const function support
Clifford Wolf
2014-06-06
*
Fixed bit-extending in $mux argument (use $bu0 instead of $pos)
Clifford Wolf
2014-02-26
*
Don't blow up constants unneccessarily in Verilog frontend
Clifford Wolf
2014-02-24
*
Added Verilog support for "`default_nettype none"
Clifford Wolf
2014-02-17
*
Correctly convert constants to RTLIL (fixed undef handling)
Clifford Wolf
2014-02-15
*
Created basic support for function calls in parameter values
Clifford Wolf
2014-02-14
*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
*
Added constant size expression support of sized constants
Clifford Wolf
2014-02-01
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