yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
*	Fixed parsing of default cases when not last case	Clifford Wolf	2013-11-18
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11
*	More undef-propagation related fixes	Clifford Wolf	2013-11-08
*	Fixed handling of power operator	Clifford Wolf	2013-11-07
*	Fixed more extend vs. extend_u0 issues	Clifford Wolf	2013-11-07
*	Renamed extend_un0() to extend_u0() and use it in genrtlil	Clifford Wolf	2013-11-07
*	Fixed const folding in corner cases with parameters	Clifford Wolf	2013-11-07
*	Fixed width detection for replicate operator	Clifford Wolf	2013-11-07
*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07
*	Fixed the fix for propagation of width hints for $signed() and $unsigned()	Clifford Wolf	2013-11-07
*	Fixed propagation of width hints for $signed() and $unsigned()	Clifford Wolf	2013-11-06
*	Additional fixes for undef propagation in concat and replicate ops	Clifford Wolf	2013-11-06
*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06
*	further improved early width and sign detection in ast simplifier	Clifford Wolf	2013-11-04
*	Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT	Clifford Wolf	2013-11-03
*	Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...	Clifford Wolf	2013-11-02
*	Various ast changes for early expression width detection (prep for constfold ...	Clifford Wolf	2013-11-02
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24
*	Fixed width and sign detection for ** operator	Clifford Wolf	2013-08-19
*	Added support for "2**n" shifter encoding	Clifford Wolf	2013-08-12
*	Added $div and $mod technology mapping	Clifford Wolf	2013-08-09
*	More fixes in ternary op sign handling	Clifford Wolf	2013-07-12
*	Fixed sign handling in ternary operator	Clifford Wolf	2013-07-12
*	Another vloghammer related bugfix	Clifford Wolf	2013-07-11
*	Fixed sign propagation in bit-wise operators	Clifford Wolf	2013-07-09
*	More fixes in ast expression sign/width handling	Clifford Wolf	2013-07-09
*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09
*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04
*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13
*	Sign-extension related fixes in SatGen and AST frontend	Clifford Wolf	2013-06-10
*	Fixes and improvements in AST const folding	Clifford Wolf	2013-06-10
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10
*	Fixed a bug in AST frontend for cases with non-blocking assigned variables as...	Clifford Wolf	2013-04-13
*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31
*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31
*	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26
*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27
*	initial import	Clifford Wolf	2013-01-05