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genrtlil.cc
Commit message (
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Author
Age
*
Correctly convert constants to RTLIL (fixed undef handling)
Clifford Wolf
2014-02-15
*
Created basic support for function calls in parameter values
Clifford Wolf
2014-02-14
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Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
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Added constant size expression support of sized constants
Clifford Wolf
2014-02-01
*
Added read_verilog -icells option
Clifford Wolf
2014-01-29
*
Added $assert cell
Clifford Wolf
2014-01-19
*
Added correct handling of $memwr priority
Clifford Wolf
2014-01-03
*
Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
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Added proper === and !== support in constant expressions
Clifford Wolf
2013-12-27
*
Various improvements in support for generate statements
Clifford Wolf
2013-12-04
*
Replaced signed_parameters API with CONST_FLAG_SIGNED
Clifford Wolf
2013-12-04
*
Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
*
Added support for local regs in named blocks
Clifford Wolf
2013-12-04
*
Fixed temp net name generation in rtlil process generator for abbreviated nam...
Clifford Wolf
2013-11-28
*
Added "src" attribute to processes
Clifford Wolf
2013-11-28
*
Added module->avail_parameters (for advanced techmap features)
Clifford Wolf
2013-11-24
*
Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
*
Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
*
Major improvements in mem2reg and added "init" sync rules
Clifford Wolf
2013-11-21
*
Fixed parsing of default cases when not last case
Clifford Wolf
2013-11-18
*
Cleanups and bugfixes in response to new internal cell checker
Clifford Wolf
2013-11-11
*
More undef-propagation related fixes
Clifford Wolf
2013-11-08
*
Fixed handling of power operator
Clifford Wolf
2013-11-07
*
Fixed more extend vs. extend_u0 issues
Clifford Wolf
2013-11-07
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Renamed extend_un0() to extend_u0() and use it in genrtlil
Clifford Wolf
2013-11-07
*
Fixed const folding in corner cases with parameters
Clifford Wolf
2013-11-07
*
Fixed width detection for replicate operator
Clifford Wolf
2013-11-07
*
Various fixes for correct parameter support
Clifford Wolf
2013-11-07
*
Fixed the fix for propagation of width hints for $signed() and $unsigned()
Clifford Wolf
2013-11-07
*
Fixed propagation of width hints for $signed() and $unsigned()
Clifford Wolf
2013-11-06
*
Additional fixes for undef propagation in concat and replicate ops
Clifford Wolf
2013-11-06
*
Improved width extension with regard to undef propagation
Clifford Wolf
2013-11-06
*
further improved early width and sign detection in ast simplifier
Clifford Wolf
2013-11-04
*
Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT
Clifford Wolf
2013-11-03
*
Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...
Clifford Wolf
2013-11-02
*
Various ast changes for early expression width detection (prep for constfold ...
Clifford Wolf
2013-11-02
*
Fixed handling of boolean attributes (frontends)
Clifford Wolf
2013-10-24
*
Fixed width and sign detection for ** operator
Clifford Wolf
2013-08-19
*
Added support for "2**n" shifter encoding
Clifford Wolf
2013-08-12
*
Added $div and $mod technology mapping
Clifford Wolf
2013-08-09
*
More fixes in ternary op sign handling
Clifford Wolf
2013-07-12
*
Fixed sign handling in ternary operator
Clifford Wolf
2013-07-12
*
Another vloghammer related bugfix
Clifford Wolf
2013-07-11
*
Fixed sign propagation in bit-wise operators
Clifford Wolf
2013-07-09
*
More fixes in ast expression sign/width handling
Clifford Wolf
2013-07-09
*
Major redesign of expr width/sign detecion (verilog/ast frontend)
Clifford Wolf
2013-07-09
*
Fixed another bug found using vloghammer
Clifford Wolf
2013-07-07
*
Added defparam support to Verilog/AST frontend
Clifford Wolf
2013-07-04
*
More fixes for bugs found using xsthammer
Clifford Wolf
2013-06-13
*
Sign-extension related fixes in SatGen and AST frontend
Clifford Wolf
2013-06-10
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