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* Correctly convert constants to RTLIL (fixed undef handling)Clifford Wolf2014-02-15
* Created basic support for function calls in parameter valuesClifford Wolf2014-02-14
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* Added constant size expression support of sized constantsClifford Wolf2014-02-01
* Added read_verilog -icells optionClifford Wolf2014-01-29
* Added $assert cellClifford Wolf2014-01-19
* Added correct handling of $memwr priorityClifford Wolf2014-01-03
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Various improvements in support for generate statementsClifford Wolf2013-12-04
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added support for local regs in named blocksClifford Wolf2013-12-04
* Fixed temp net name generation in rtlil process generator for abbreviated nam...Clifford Wolf2013-11-28
* Added "src" attribute to processesClifford Wolf2013-11-28
* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Fixed parsing of default cases when not last caseClifford Wolf2013-11-18
* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
* More undef-propagation related fixesClifford Wolf2013-11-08
* Fixed handling of power operatorClifford Wolf2013-11-07
* Fixed more extend vs. extend_u0 issuesClifford Wolf2013-11-07
* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-07
* Fixed const folding in corner cases with parametersClifford Wolf2013-11-07
* Fixed width detection for replicate operatorClifford Wolf2013-11-07
* Various fixes for correct parameter supportClifford Wolf2013-11-07
* Fixed the fix for propagation of width hints for $signed() and $unsigned()Clifford Wolf2013-11-07
* Fixed propagation of width hints for $signed() and $unsigned()Clifford Wolf2013-11-06
* Additional fixes for undef propagation in concat and replicate opsClifford Wolf2013-11-06
* Improved width extension with regard to undef propagationClifford Wolf2013-11-06
* further improved early width and sign detection in ast simplifierClifford Wolf2013-11-04
* Fixed detectSignWidthWorker (ast frontend) for AST_CONCATClifford Wolf2013-11-03
* Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...Clifford Wolf2013-11-02
* Various ast changes for early expression width detection (prep for constfold ...Clifford Wolf2013-11-02
* Fixed handling of boolean attributes (frontends)Clifford Wolf2013-10-24
* Fixed width and sign detection for ** operatorClifford Wolf2013-08-19
* Added support for "2**n" shifter encodingClifford Wolf2013-08-12
* Added $div and $mod technology mappingClifford Wolf2013-08-09
* More fixes in ternary op sign handlingClifford Wolf2013-07-12
* Fixed sign handling in ternary operatorClifford Wolf2013-07-12
* Another vloghammer related bugfixClifford Wolf2013-07-11
* Fixed sign propagation in bit-wise operatorsClifford Wolf2013-07-09
* More fixes in ast expression sign/width handlingClifford Wolf2013-07-09
* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
* Fixed another bug found using vloghammerClifford Wolf2013-07-07
* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
* Sign-extension related fixes in SatGen and AST frontendClifford Wolf2013-06-10