summaryrefslogtreecommitdiff
path: root/frontends/ast/genrtlil.cc
Commit message (Collapse)AuthorAge
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
|
* Fixed assignment of out-of bounds array elementClifford Wolf2014-09-06
|
* Removed $bu0 cell typeClifford Wolf2014-09-04
|
* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-21
|
* Improved AST ProcessGenerator performanceClifford Wolf2014-08-17
|
* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-17
|
* AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-16
|
* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-14
|
* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-14
|
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
|
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
|
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
|
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
|
* Removed left over debug codeClifford Wolf2014-07-28
|
* Fixed part selects of parametersClifford Wolf2014-07-28
|
* Set results of out-of-bounds static bit/part select to undefClifford Wolf2014-07-28
|
* Fixed RTLIL code generator for part select of parameterClifford Wolf2014-07-28
|
* Fixed width detection for part selectsClifford Wolf2014-07-28
|
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
|
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
|
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
|
* Fixed signdness detection of expressions with bit- and part-selectsClifford Wolf2014-07-28
|
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
|
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
|
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
|
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
|
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
|
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
|
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
|
* SigSpec refactoring: More cleanups of old SigSpec use patternClifford Wolf2014-07-22
|
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-22
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-22
|
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
|
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
|
* changes in verilog frontend for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
|
* More found_real-related fixes to AstNode::detectSignWidthWorkerClifford Wolf2014-06-24
|
* fixed signdness detection for expressions with realsClifford Wolf2014-06-21
|
* Added found_real feature to AstNode::detectSignWidthClifford Wolf2014-06-16
|
* improved (fixed) conversion of real values to bit vectorsClifford Wolf2014-06-14
|
* Added real->int convertion in ast genrtlilClifford Wolf2014-06-14
|
* further improved const function supportClifford Wolf2014-06-07
|
* improved const function supportClifford Wolf2014-06-06
|
* Fixed bit-extending in $mux argument (use $bu0 instead of $pos)Clifford Wolf2014-02-26
|
* Don't blow up constants unneccessarily in Verilog frontendClifford Wolf2014-02-24
|
* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-17
|
* Correctly convert constants to RTLIL (fixed undef handling)Clifford Wolf2014-02-15
|
* Created basic support for function calls in parameter valuesClifford Wolf2014-02-14
|
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
|
* Added constant size expression support of sized constantsClifford Wolf2014-02-01
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-23 16:24:04 +0000