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* Fixed width and sign detection for ** operatorClifford Wolf2013-08-19
* Added support for "2**n" shifter encodingClifford Wolf2013-08-12
* Added $div and $mod technology mappingClifford Wolf2013-08-09
* More fixes in ternary op sign handlingClifford Wolf2013-07-12
* Fixed sign handling in ternary operatorClifford Wolf2013-07-12
* Another vloghammer related bugfixClifford Wolf2013-07-11
* Fixed sign propagation in bit-wise operatorsClifford Wolf2013-07-09
* More fixes in ast expression sign/width handlingClifford Wolf2013-07-09
* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
* Fixed another bug found using vloghammerClifford Wolf2013-07-07
* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
* Sign-extension related fixes in SatGen and AST frontendClifford Wolf2013-06-10
* Fixes and improvements in AST const foldingClifford Wolf2013-06-10
* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-10
* Fixed a bug in AST frontend for cases with non-blocking assigned variables as...Clifford Wolf2013-04-13
* Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-31
* Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
* Fixed handling of unconditional generate blocksClifford Wolf2013-03-26
* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-25
* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-27
* initial importClifford Wolf2013-01-05