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* Imported yosys 0.7Ruben Undheim2016-11-03
* Squashed commit of the following:Ruben Undheim2016-09-23
* Fixed some visual studio warningsClifford Wolf2016-02-13
* genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSi...Rick Altherr2016-01-31
* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-11
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-25
* Added read-enable to memory modelClifford Wolf2015-09-25
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-14
* Added WORDS parameter to $meminitClifford Wolf2015-07-31
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()Clifford Wolf2015-03-01
* Added non-std verilog assume() statementClifford Wolf2015-02-26
* Convert floating point cell parameters to stringsClifford Wolf2015-02-18
* Various fixes for memories with offsetsClifford Wolf2015-02-14
* Creating $meminit cells in verilog front-endClifford Wolf2015-02-14
* Ignore explicit assignments to constants in HDL codeClifford Wolf2015-02-08
* Fixed a bug with autowire bit sizeClifford Wolf2015-02-08
* Fixed memory->start_offset handlingClifford Wolf2015-01-01
* Changed more code to dict<> and pool<>Clifford Wolf2014-12-28
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-24
* Added log_warning() APIClifford Wolf2014-11-09
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* Fixed assignment of out-of bounds array elementClifford Wolf2014-09-06
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-21
* Improved AST ProcessGenerator performanceClifford Wolf2014-08-17
* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-17
* AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-16
* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-14
* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-14
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Removed left over debug codeClifford Wolf2014-07-28
* Fixed part selects of parametersClifford Wolf2014-07-28
* Set results of out-of-bounds static bit/part select to undefClifford Wolf2014-07-28
* Fixed RTLIL code generator for part select of parameterClifford Wolf2014-07-28
* Fixed width detection for part selectsClifford Wolf2014-07-28
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Fixed signdness detection of expressions with bit- and part-selectsClifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24