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genrtlil.cc
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Author
Age
*
Imported yosys 0.7
Ruben Undheim
2016-11-03
*
Squashed commit of the following:
Ruben Undheim
2016-09-23
*
Fixed some visual studio warnings
Clifford Wolf
2016-02-13
*
genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSi...
Rick Altherr
2016-01-31
*
Fixed handling of parameters and localparams in functions
Clifford Wolf
2015-11-11
*
Import more std:: stuff into Yosys namespace
Clifford Wolf
2015-10-25
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Added read-enable to memory model
Clifford Wolf
2015-09-25
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Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
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Added WORDS parameter to $meminit
Clifford Wolf
2015-07-31
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()
Clifford Wolf
2015-03-01
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Added non-std verilog assume() statement
Clifford Wolf
2015-02-26
*
Convert floating point cell parameters to strings
Clifford Wolf
2015-02-18
*
Various fixes for memories with offsets
Clifford Wolf
2015-02-14
*
Creating $meminit cells in verilog front-end
Clifford Wolf
2015-02-14
*
Ignore explicit assignments to constants in HDL code
Clifford Wolf
2015-02-08
*
Fixed a bug with autowire bit size
Clifford Wolf
2015-02-08
*
Fixed memory->start_offset handling
Clifford Wolf
2015-01-01
*
Changed more code to dict<> and pool<>
Clifford Wolf
2014-12-28
*
Renamed extend() to extend_xx(), changed most users to extend_u0()
Clifford Wolf
2014-12-24
*
Added log_warning() API
Clifford Wolf
2014-11-09
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Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
*
Fixed assignment of out-of bounds array element
Clifford Wolf
2014-09-06
*
Removed $bu0 cell type
Clifford Wolf
2014-09-04
*
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
Clifford Wolf
2014-08-21
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Improved AST ProcessGenerator performance
Clifford Wolf
2014-08-17
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Use stackmap<> in AST ProcessGenerator
Clifford Wolf
2014-08-17
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AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
Clifford Wolf
2014-08-16
*
Added RTLIL::SigSpec::to_sigbit_map()
Clifford Wolf
2014-08-14
*
Changed the AST genWidthRTLIL subst interface to use a std::map
Clifford Wolf
2014-08-14
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
*
Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
*
Removed left over debug code
Clifford Wolf
2014-07-28
*
Fixed part selects of parameters
Clifford Wolf
2014-07-28
*
Set results of out-of-bounds static bit/part select to undef
Clifford Wolf
2014-07-28
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Fixed RTLIL code generator for part select of parameter
Clifford Wolf
2014-07-28
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Fixed width detection for part selects
Clifford Wolf
2014-07-28
*
Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
*
Added wire->upto flag for signals such as "wire [0:7] x;"
Clifford Wolf
2014-07-28
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Fixed signdness detection of expressions with bit- and part-selects
Clifford Wolf
2014-07-28
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Replaced more old SigChunk programming patterns
Clifford Wolf
2014-07-24
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