yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
...
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
*	SigSpec refactoring: More cleanups of old SigSpec use pattern	Clifford Wolf	2014-07-22
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	changes in verilog frontend for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16
*	More found_real-related fixes to AstNode::detectSignWidthWorker	Clifford Wolf	2014-06-24
*	fixed signdness detection for expressions with reals	Clifford Wolf	2014-06-21
*	Added found_real feature to AstNode::detectSignWidth	Clifford Wolf	2014-06-16
*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14
*	Added real->int convertion in ast genrtlil	Clifford Wolf	2014-06-14
*	further improved const function support	Clifford Wolf	2014-06-07
*	improved const function support	Clifford Wolf	2014-06-06
*	Fixed bit-extending in $mux argument (use $bu0 instead of $pos)	Clifford Wolf	2014-02-26
*	Don't blow up constants unneccessarily in Verilog frontend	Clifford Wolf	2014-02-24
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17
*	Correctly convert constants to RTLIL (fixed undef handling)	Clifford Wolf	2014-02-15
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29
*	Added $assert cell	Clifford Wolf	2014-01-19
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04
*	Fixed temp net name generation in rtlil process generator for abbreviated nam...	Clifford Wolf	2013-11-28
*	Added "src" attribute to processes	Clifford Wolf	2013-11-28
*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
*	Fixed parsing of default cases when not last case	Clifford Wolf	2013-11-18
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11
*	More undef-propagation related fixes	Clifford Wolf	2013-11-08
*	Fixed handling of power operator	Clifford Wolf	2013-11-07
*	Fixed more extend vs. extend_u0 issues	Clifford Wolf	2013-11-07
*	Renamed extend_un0() to extend_u0() and use it in genrtlil	Clifford Wolf	2013-11-07
*	Fixed const folding in corner cases with parameters	Clifford Wolf	2013-11-07
*	Fixed width detection for replicate operator	Clifford Wolf	2013-11-07