yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Fixed handling of re-declarations of wires in tasks and functions	Clifford Wolf	2015-11-23
*	More bugfixes in handling of parameters in tasks and functions	Clifford Wolf	2015-11-12
*	Fixed handling of parameters and localparams in functions	Clifford Wolf	2015-11-11
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25
*	Fixed complexity of assigning to vectors in constant functions	Clifford Wolf	2015-10-01
*	Fixed detection of unconditional $readmem[hb]	Clifford Wolf	2015-09-30
*	Bugfixes in $readmem[hb]	Clifford Wolf	2015-09-25
*	Bugfix in handling of multi-dimensional memories	Clifford Wolf	2015-09-23
*	Warning for $display/$write outside initial block	Clifford Wolf	2015-09-23
*	Fixed multi-level prefix resolving	Clifford Wolf	2015-09-22
*	Improvements to $display system task	Andrew Zonenberg	2015-09-19
*	Added AST_INITIAL checks for $finish and $display	Clifford Wolf	2015-09-18
*	Initial implementation of $display()	Andrew Zonenberg	2015-09-18
*	Initial implementation of $finish()	Andrew Zonenberg	2015-09-18
*	Fixed handling of memory read without address	Clifford Wolf	2015-08-22
*	Keep gcc from complaining about uninitialized variables	Larry Doolittle	2015-08-14
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14
*	Added WORDS parameter to $meminit	Clifford Wolf	2015-07-31
*	Fixed nested mem2reg	Clifford Wolf	2015-07-29
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
*	Fixed handling of parameters with reversed range	Clifford Wolf	2015-06-08
*	Fixed signedness of genvar expressions	Clifford Wolf	2015-05-29
*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26
*	Added deep recursion warning to AST simplify	Clifford Wolf	2015-02-20
*	Parser support for complex delay expressions	Clifford Wolf	2015-02-20
*	Various fixes for memories with offsets	Clifford Wolf	2015-02-14
*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14
*	Creating $meminit cells in verilog front-end	Clifford Wolf	2015-02-14
*	Added AstNode::simplify() recursion counter	Clifford Wolf	2015-02-13
*	Added ENABLE_NDEBUG makefile options	Clifford Wolf	2015-01-24
*	Ignoring more system task and functions	Clifford Wolf	2015-01-15
*	Fixed handling of "input foo; reg [0:0] foo;"	Clifford Wolf	2015-01-15
*	Consolidate "Blocking assignment to memory.." msgs for the same line	Clifford Wolf	2015-01-15
*	dict/pool changes in ast	Clifford Wolf	2014-12-29
*	Fixed mem2reg warning message	Clifford Wolf	2014-12-27
*	Added log_warning() API	Clifford Wolf	2014-11-09
*	AST simplifier: optimize constant AST_CASE nodes before recursively descending	Clifford Wolf	2014-10-29
*	Improvements in $readmem[bh] implementation	Clifford Wolf	2014-10-26
*	Added support for $readmemh/$readmemb	Clifford Wolf	2014-10-26
*	Fixed various VS warnings	Clifford Wolf	2014-10-18
*	Wrapped math in int constructor	William Speirs	2014-10-17
*	Fixed handling of invalid array access in mem2reg code	Clifford Wolf	2014-10-16
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	Another $clog2 bugfix	Clifford Wolf	2014-09-08
*	Fixed $clog2 (off by one error)	Clifford Wolf	2014-09-06
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
*	Fixed small memory leak in ast simplify	Clifford Wolf	2014-08-21
*	Added support for DPI function with different names in C and Verilog	Clifford Wolf	2014-08-21
*	Fixed memory leak in DPI function calls	Clifford Wolf	2014-08-21
*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21