yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04
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*	Fixes and improvements in AST const folding	Clifford Wolf	2013-06-10
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*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10
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*	Merge branch 'bugfix'	Clifford Wolf	2013-05-16
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\| *	Fixed synthesis of functions in latched blocks	Clifford Wolf	2013-05-16
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* \|	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31
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* \|	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26
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* \|	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26
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*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25
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*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24
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*	Another fix in mem2reg ast simplify logic	Clifford Wolf	2013-03-24
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*	Improved mem2reg handling in ast simplifier	Clifford Wolf	2013-03-24
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*	Tiny fixes to verilog parser	Clifford Wolf	2013-03-23
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*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27
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*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26
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*	initial import	Clifford Wolf	2013-01-05