summaryrefslogtreecommitdiff
path: root/frontends/ast
Commit message (Expand)AuthorAge
* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-05
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-02
* Replaced sha1 implementationClifford Wolf2014-08-01
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Removed left over debug codeClifford Wolf2014-07-28
* Fixed part selects of parametersClifford Wolf2014-07-28
* Set results of out-of-bounds static bit/part select to undefClifford Wolf2014-07-28
* Fixed RTLIL code generator for part select of parameterClifford Wolf2014-07-28
* Fixed width detection for part selectsClifford Wolf2014-07-28
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Fixed signdness detection of expressions with bit- and part-selectsClifford Wolf2014-07-28
* Added proper Design->addModule interfaceClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Fixed two memory leaks in ast simplifyClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* Various small fixes (from gcc compiler warnings)Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* SigSpec refactoring: More cleanups of old SigSpec use patternClifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::size() to be read-onlyClifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-17
* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-17
* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-17
* changes in verilog frontend for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-16
* Fixed processing of initial values for block-local variablesClifford Wolf2014-07-11
* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-25
* More found_real-related fixes to AstNode::detectSignWidthWorkerClifford Wolf2014-06-24
* fixed signdness detection for expressions with realsClifford Wolf2014-06-21
* Added AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-17
* Improved handling of relational op of real valuesClifford Wolf2014-06-17
* Improved ternary support for real valuesClifford Wolf2014-06-16
* Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012Clifford Wolf2014-06-16
* Added found_real feature to AstNode::detectSignWidthClifford Wolf2014-06-16
* Improved AstNode::realAsConst for large numbersClifford Wolf2014-06-15
* Improved AstNode::asReal for large integersClifford Wolf2014-06-15