yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11
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*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
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*	namespace Yosys	Clifford Wolf	2014-09-27
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*	Another $clog2 bugfix	Clifford Wolf	2014-09-08
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*	Fixed $clog2 (off by one error)	Clifford Wolf	2014-09-06
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*	Fixed assignment of out-of bounds array element	Clifford Wolf	2014-09-06
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*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
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*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22
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*	Archibald Rust and Clifford Wolf: ffi-based dpi_call()	Clifford Wolf	2014-08-22
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*	Fixed small memory leak in ast simplify	Clifford Wolf	2014-08-21
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*	Added support for DPI function with different names in C and Verilog	Clifford Wolf	2014-08-21
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*	Added AstNode::asInt()	Clifford Wolf	2014-08-21
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*	Fixed memory leak in DPI function calls	Clifford Wolf	2014-08-21
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*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21
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*	Added support for global tasks and functions	Clifford Wolf	2014-08-21
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*	Added "via_celltype" attribute on task/func	Clifford Wolf	2014-08-18
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*	Added const folding of AST_CASE to AST simplifier	Clifford Wolf	2014-08-18
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*	Improved AST ProcessGenerator performance	Clifford Wolf	2014-08-17
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*	Use stackmap<> in AST ProcessGenerator	Clifford Wolf	2014-08-17
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*	AST ProcessGenerator: replaced subst__{from,to} with subst__map	Clifford Wolf	2014-08-16
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*	Fixed bug in "read_verilog -ignore_redef"	Clifford Wolf	2014-08-15
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*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14
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*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14
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*	Fixed handling of task outputs	Clifford Wolf	2014-08-14
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*	Added module->ports	Clifford Wolf	2014-08-14
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*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06
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*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05
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*	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
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*	Replaced sha1 implementation	Clifford Wolf	2014-08-01
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
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*	Removed left over debug code	Clifford Wolf	2014-07-28
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*	Fixed part selects of parameters	Clifford Wolf	2014-07-28
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*	Set results of out-of-bounds static bit/part select to undef	Clifford Wolf	2014-07-28
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*	Fixed RTLIL code generator for part select of parameter	Clifford Wolf	2014-07-28
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*	Fixed width detection for part selects	Clifford Wolf	2014-07-28
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*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
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*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Fixed signdness detection of expressions with bit- and part-selects	Clifford Wolf	2014-07-28
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*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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