yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
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*	Fixed relational operators for const real expressions	Clifford Wolf	2014-06-14
*	Added support for math functions	Clifford Wolf	2014-06-14
*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14
*	Implemented more real arithmetic	Clifford Wolf	2014-06-14
*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14
*	Added real->int convertion in ast genrtlil	Clifford Wolf	2014-06-14
*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13
*	Add support for cell arrays	Clifford Wolf	2014-06-07
*	Added support for repeat stmt in const functions	Clifford Wolf	2014-06-07
*	further improved const function support	Clifford Wolf	2014-06-07
*	improved const function support	Clifford Wolf	2014-06-06
*	fix functions with no block (but single statement, loop, etc.)	Clifford Wolf	2014-06-06
*	improved ast simplify of const functions	Clifford Wolf	2014-06-06
*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06
*	Include id2ast pointers when dumping AST	Clifford Wolf	2014-03-05
*	Fixed merging of compatible wire decls in AST frontend	Clifford Wolf	2014-03-05
*	Bugfix in recursive AST simplification	Clifford Wolf	2014-03-05
*	Fixed bit-extending in $mux argument (use $bu0 instead of $pos)	Clifford Wolf	2014-02-26
*	Don't blow up constants unneccessarily in Verilog frontend	Clifford Wolf	2014-02-24
*	Fixed bug in generation of undefs for $memwr MUXes	Clifford Wolf	2014-02-22
*	Cleanups in handling of read_verilog -defer and -icells	Clifford Wolf	2014-02-20
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17
*	Improved support for constant functions	Clifford Wolf	2014-02-16
*	Correctly convert constants to RTLIL (fixed undef handling)	Clifford Wolf	2014-02-15
*	Be more conservative with new const-function code	Clifford Wolf	2014-02-14
*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13
*	Fixed gcc compiler warnings with release build	Clifford Wolf	2014-02-06
*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01
*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29
*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20
*	Added $assert cell	Clifford Wolf	2014-01-19
*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19
*	Fixed typo in frontends/ast/simplify.cc	Clifford Wolf	2014-01-12
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03
*	Fixed a stupid access after delete bug	Clifford Wolf	2013-12-29
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05
*	Added const folding support for $signed and $unsigned	Clifford Wolf	2013-12-05
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05
*	Fixed generate-for (and disabled double warning for auto-wire)	Clifford Wolf	2013-12-04
*	Added support for $clog2 system function	Clifford Wolf	2013-12-04
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04