yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06
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*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05
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*	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
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*	Replaced sha1 implementation	Clifford Wolf	2014-08-01
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
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*	Removed left over debug code	Clifford Wolf	2014-07-28
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*	Fixed part selects of parameters	Clifford Wolf	2014-07-28
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*	Set results of out-of-bounds static bit/part select to undef	Clifford Wolf	2014-07-28
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*	Fixed RTLIL code generator for part select of parameter	Clifford Wolf	2014-07-28
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*	Fixed width detection for part selects	Clifford Wolf	2014-07-28
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*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
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*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Fixed signdness detection of expressions with bit- and part-selects	Clifford Wolf	2014-07-28
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*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
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*	Fixed two memory leaks in ast simplify	Clifford Wolf	2014-07-25
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
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*	Various small fixes (from gcc compiler warnings)	Clifford Wolf	2014-07-23
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
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*	SigSpec refactoring: More cleanups of old SigSpec use pattern	Clifford Wolf	2014-07-22
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	Clifford Wolf	2014-07-22
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
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*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17
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*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17
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*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17
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*	changes in verilog frontend for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16
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*	Fixed processing of initial values for block-local variables	Clifford Wolf	2014-07-11
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*	Fixed handling of mixed real/int ternary expressions	Clifford Wolf	2014-06-25
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*	More found_real-related fixes to AstNode::detectSignWidthWorker	Clifford Wolf	2014-06-24
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*	fixed signdness detection for expressions with reals	Clifford Wolf	2014-06-21
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*	Added AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17
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*	Improved handling of relational op of real values	Clifford Wolf	2014-06-17
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*	Improved ternary support for real values	Clifford Wolf	2014-06-16
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*	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	Clifford Wolf	2014-06-16
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*	Added found_real feature to AstNode::detectSignWidth	Clifford Wolf	2014-06-16
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