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* Added read_verilog -icells optionClifford Wolf2014-01-29
* Fixed algorithmic complexity of AST simplification of long expressionsClifford Wolf2014-01-20
* Added $assert cellClifford Wolf2014-01-19
* Added Verilog parser support for assertsClifford Wolf2014-01-19
* Fixed typo in frontends/ast/simplify.ccClifford Wolf2014-01-12
* Added correct handling of $memwr priorityClifford Wolf2014-01-03
* Fixed a stupid access after delete bugClifford Wolf2013-12-29
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Keep strings as strings in const ternary and concatClifford Wolf2013-12-05
* Added const folding support for $signed and $unsignedClifford Wolf2013-12-05
* Added AstNode::mkconst_str APIClifford Wolf2013-12-05
* Fixed generate-for (and disabled double warning for auto-wire)Clifford Wolf2013-12-04
* Added support for $clog2 system functionClifford Wolf2013-12-04
* Various improvements in support for generate statementsClifford Wolf2013-12-04
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added support for local regs in named blocksClifford Wolf2013-12-04
* Fixed temp net name generation in rtlil process generator for abbreviated nam...Clifford Wolf2013-11-28
* Added "src" attribute to processesClifford Wolf2013-11-28
* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-24
* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
* Early wire/reg/parameter width calculation in ast/simplifyClifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Fixed async proc detection in mem2regClifford Wolf2013-11-21
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Another name resolution bugfix for generate blocksClifford Wolf2013-11-20
* Do not allow memory bit select on the left side of an assignmentClifford Wolf2013-11-20
* Fixed name resolution of local tasks and functions in generate blockClifford Wolf2013-11-20
* Implemented part/bit select on memory readClifford Wolf2013-11-20
* Fixed two bugs in mem2reg functionality in AST frontendClifford Wolf2013-11-18
* Added dumping of attributes in AST frontendClifford Wolf2013-11-18
* Fixed parsing of default cases when not last caseClifford Wolf2013-11-18
* Fixed mem2reg for reg usage outside always blockClifford Wolf2013-11-18
* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
* Call internal checker more oftenClifford Wolf2013-11-10
* More undef-propagation related fixesClifford Wolf2013-11-08
* Fixed handling of different signedness in power operandsClifford Wolf2013-11-08
* Implemented const folding of ternary op with undef selectClifford Wolf2013-11-08
* Fixed handling of power operatorClifford Wolf2013-11-07
* Fixed more extend vs. extend_u0 issuesClifford Wolf2013-11-07
* Disabled const folding of ternary op when select is undefClifford Wolf2013-11-07
* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-07
* Fixed sign handling in constantsClifford Wolf2013-11-07
* Fixed const folding in corner cases with parametersClifford Wolf2013-11-07
* Fixed width detection for replicate operatorClifford Wolf2013-11-07
* Fixed at_zero evaluation of dynamic rangesClifford Wolf2013-11-07
* Various fixes for correct parameter supportClifford Wolf2013-11-07