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* genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSi...Rick Altherr2016-01-31
* Fixed handling of re-declarations of wires in tasks and functionsClifford Wolf2015-11-23
* More bugfixes in handling of parameters in tasks and functionsClifford Wolf2015-11-12
* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-11
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-25
* Fixed complexity of assigning to vectors in constant functionsClifford Wolf2015-10-01
* Fixed detection of unconditional $readmem[hb]Clifford Wolf2015-09-30
* Bugfixes in $readmem[hb]Clifford Wolf2015-09-25
* Fixed segfault in AstNode::asRealClifford Wolf2015-09-25
* Added read-enable to memory modelClifford Wolf2015-09-25
* Fixed AstNode::mkconst_bits() segfault on zero-sized constantClifford Wolf2015-09-24
* Bugfix in handling of multi-dimensional memoriesClifford Wolf2015-09-23
* Warning for $display/$write outside initial blockClifford Wolf2015-09-23
* Fixed multi-level prefix resolvingClifford Wolf2015-09-22
* Improvements to $display system taskAndrew Zonenberg2015-09-19
* Added AST_INITIAL checks for $finish and $displayClifford Wolf2015-09-18
* Initial implementation of $display()Andrew Zonenberg2015-09-18
* Initial implementation of $finish()Andrew Zonenberg2015-09-18
* Fixed handling of memory read without addressClifford Wolf2015-08-22
* Another block of spelling fixesLarry Doolittle2015-08-14
* Keep gcc from complaining about uninitialized variablesLarry Doolittle2015-08-14
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-14
* Added WORDS parameter to $meminitClifford Wolf2015-07-31
* Fixed nested mem2regClifford Wolf2015-07-29
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Fixed handling of parameters with reversed rangeClifford Wolf2015-06-08
* Fixed signedness of genvar expressionsClifford Wolf2015-05-29
* Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()Clifford Wolf2015-03-01
* Added non-std verilog assume() statementClifford Wolf2015-02-26
* Added deep recursion warning to AST simplifyClifford Wolf2015-02-20
* Parser support for complex delay expressionsClifford Wolf2015-02-20
* Convert floating point cell parameters to stringsClifford Wolf2015-02-18
* Various fixes for memories with offsetsClifford Wolf2015-02-14
* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-14
* Creating $meminit cells in verilog front-endClifford Wolf2015-02-14
* Added AstNode::simplify() recursion counterClifford Wolf2015-02-13
* Ignore explicit assignments to constants in HDL codeClifford Wolf2015-02-08
* Fixed a bug with autowire bit sizeClifford Wolf2015-02-08
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-24
* Ignoring more system task and functionsClifford Wolf2015-01-15
* Fixed handling of "input foo; reg [0:0] foo;"Clifford Wolf2015-01-15
* Consolidate "Blocking assignment to memory.." msgs for the same lineClifford Wolf2015-01-15
* Fixed memory->start_offset handlingClifford Wolf2015-01-01
* Added global yosys_celltypesClifford Wolf2014-12-29
* dict/pool changes in astClifford Wolf2014-12-29
* Changed more code to dict<> and pool<>Clifford Wolf2014-12-28
* Fixed mem2reg warning messageClifford Wolf2014-12-27
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-24
* Added log_warning() APIClifford Wolf2014-11-09