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* fix functions with no block (but single statement, loop, etc.)Clifford Wolf2014-06-06
* improved ast simplify of const functionsClifford Wolf2014-06-06
* added while and repeat support to verilog parserClifford Wolf2014-06-06
* Include id2ast pointers when dumping ASTClifford Wolf2014-03-05
* Fixed merging of compatible wire decls in AST frontendClifford Wolf2014-03-05
* Bugfix in recursive AST simplificationClifford Wolf2014-03-05
* Fixed bit-extending in $mux argument (use $bu0 instead of $pos)Clifford Wolf2014-02-26
* Don't blow up constants unneccessarily in Verilog frontendClifford Wolf2014-02-24
* Fixed bug in generation of undefs for $memwr MUXesClifford Wolf2014-02-22
* Cleanups in handling of read_verilog -defer and -icellsClifford Wolf2014-02-20
* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-17
* Improved support for constant functionsClifford Wolf2014-02-16
* Correctly convert constants to RTLIL (fixed undef handling)Clifford Wolf2014-02-15
* Be more conservative with new const-function codeClifford Wolf2014-02-14
* Added support for FOR loops in function calls in parametersClifford Wolf2014-02-14
* Created basic support for function calls in parameter valuesClifford Wolf2014-02-14
* Implemented read_verilog -deferClifford Wolf2014-02-13
* Fixed gcc compiler warnings with release buildClifford Wolf2014-02-06
* Fixed bug in sequential sat proofs and improved handling of assertsClifford Wolf2014-02-04
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* Added constant size expression support of sized constantsClifford Wolf2014-02-01
* Bugfix in name resolution with generate blocksClifford Wolf2014-01-30
* Added read_verilog -icells optionClifford Wolf2014-01-29
* Fixed algorithmic complexity of AST simplification of long expressionsClifford Wolf2014-01-20
* Added $assert cellClifford Wolf2014-01-19
* Added Verilog parser support for assertsClifford Wolf2014-01-19
* Fixed typo in frontends/ast/simplify.ccClifford Wolf2014-01-12
* Added correct handling of $memwr priorityClifford Wolf2014-01-03
* Fixed a stupid access after delete bugClifford Wolf2013-12-29
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Keep strings as strings in const ternary and concatClifford Wolf2013-12-05
* Added const folding support for $signed and $unsignedClifford Wolf2013-12-05
* Added AstNode::mkconst_str APIClifford Wolf2013-12-05
* Fixed generate-for (and disabled double warning for auto-wire)Clifford Wolf2013-12-04
* Added support for $clog2 system functionClifford Wolf2013-12-04
* Various improvements in support for generate statementsClifford Wolf2013-12-04
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added support for local regs in named blocksClifford Wolf2013-12-04
* Fixed temp net name generation in rtlil process generator for abbreviated nam...Clifford Wolf2013-11-28
* Added "src" attribute to processesClifford Wolf2013-11-28
* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-24
* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
* Early wire/reg/parameter width calculation in ast/simplifyClifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Fixed async proc detection in mem2regClifford Wolf2013-11-21
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21