yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Improved support for constant functions	Clifford Wolf	2014-02-16
*	Correctly convert constants to RTLIL (fixed undef handling)	Clifford Wolf	2014-02-15
*	Be more conservative with new const-function code	Clifford Wolf	2014-02-14
*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13
*	Fixed gcc compiler warnings with release build	Clifford Wolf	2014-02-06
*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01
*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29
*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20
*	Added $assert cell	Clifford Wolf	2014-01-19
*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19
*	Fixed typo in frontends/ast/simplify.cc	Clifford Wolf	2014-01-12
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03
*	Fixed a stupid access after delete bug	Clifford Wolf	2013-12-29
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05
*	Added const folding support for $signed and $unsigned	Clifford Wolf	2013-12-05
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05
*	Fixed generate-for (and disabled double warning for auto-wire)	Clifford Wolf	2013-12-04
*	Added support for $clog2 system function	Clifford Wolf	2013-12-04
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04
*	Fixed temp net name generation in rtlil process generator for abbreviated nam...	Clifford Wolf	2013-11-28
*	Added "src" attribute to processes	Clifford Wolf	2013-11-28
*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24
*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24
*	Early wire/reg/parameter width calculation in ast/simplify	Clifford Wolf	2013-11-24
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
*	Fixed async proc detection in mem2reg	Clifford Wolf	2013-11-21
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
*	Another name resolution bugfix for generate blocks	Clifford Wolf	2013-11-20
*	Do not allow memory bit select on the left side of an assignment	Clifford Wolf	2013-11-20
*	Fixed name resolution of local tasks and functions in generate block	Clifford Wolf	2013-11-20
*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20
*	Fixed two bugs in mem2reg functionality in AST frontend	Clifford Wolf	2013-11-18
*	Added dumping of attributes in AST frontend	Clifford Wolf	2013-11-18
*	Fixed parsing of default cases when not last case	Clifford Wolf	2013-11-18
*	Fixed mem2reg for reg usage outside always block	Clifford Wolf	2013-11-18
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11
*	Call internal checker more often	Clifford Wolf	2013-11-10
*	More undef-propagation related fixes	Clifford Wolf	2013-11-08