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* Various ast changes for early expression width detection (prep for constfold ↵Clifford Wolf2013-11-02
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* Fixed handling of boolean attributes (frontends)Clifford Wolf2013-10-24
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* Added support for notif0/notif1 primitivesJohann Glaser2013-08-20
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* Fixed width and sign detection for ** operatorClifford Wolf2013-08-19
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* Added support for bufif0/bufif1 primitivesClifford Wolf2013-08-19
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* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-19
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* Added support for "2**n" shifter encodingClifford Wolf2013-08-12
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* Added $div and $mod technology mappingClifford Wolf2013-08-09
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* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-27
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* More fixes in ternary op sign handlingClifford Wolf2013-07-12
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* Fixed sign handling in ternary operatorClifford Wolf2013-07-12
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* Another vloghammer related bugfixClifford Wolf2013-07-11
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* Fixed sign propagation in bit-wise operatorsClifford Wolf2013-07-09
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* More fixes in ast expression sign/width handlingClifford Wolf2013-07-09
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* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
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* Fixed another bug found using vloghammerClifford Wolf2013-07-07
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* Fixed AST_CONSTANT node generationClifford Wolf2013-07-07
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* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
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* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
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* Sign-extension related fixes in SatGen and AST frontendClifford Wolf2013-06-10
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* Fixes and improvements in AST const foldingClifford Wolf2013-06-10
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* Enabled AST/Verilog front-end optimizations per defaultClifford Wolf2013-06-10
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* Added log_assert() apiClifford Wolf2013-05-24
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* Merge branch 'bugfix'Clifford Wolf2013-05-16
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| * Fixed synthesis of functions in latched blocksClifford Wolf2013-05-16
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* | Fixed handling of positional module parametersClifford Wolf2013-04-26
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* | Only use sha1 checksums for names of parametric modules when the verbose ↵Clifford Wolf2013-04-26
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* | Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵Clifford Wolf2013-04-13
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* | Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-31
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* | Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-31
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* | Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
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* | Improvements and bugfixes for generate blocks with local signalsClifford Wolf2013-03-26
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* | Fixed handling of unconditional generate blocksClifford Wolf2013-03-26
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* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-25
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* Added mem2reg option to verilog frontendClifford Wolf2013-03-24
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* Another fix in mem2reg ast simplify logicClifford Wolf2013-03-24
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* Improved mem2reg handling in ast simplifierClifford Wolf2013-03-24
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* Tiny fixes to verilog parserClifford Wolf2013-03-23
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* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-27
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* Added support for verilog genblock[index].member syntaxClifford Wolf2013-02-26
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* initial importClifford Wolf2013-01-05