yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	AST ProcessGenerator: replaced subst__{from,to} with subst__map	Clifford Wolf	2014-08-16
*	Fixed bug in "read_verilog -ignore_redef"	Clifford Wolf	2014-08-15
*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14
*	Fixed handling of task outputs	Clifford Wolf	2014-08-14
*	Added module->ports	Clifford Wolf	2014-08-14
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06
*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05
*	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
*	Removed left over debug code	Clifford Wolf	2014-07-28
*	Fixed part selects of parameters	Clifford Wolf	2014-07-28
*	Set results of out-of-bounds static bit/part select to undef	Clifford Wolf	2014-07-28
*	Fixed RTLIL code generator for part select of parameter	Clifford Wolf	2014-07-28
*	Fixed width detection for part selects	Clifford Wolf	2014-07-28
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28
*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Fixed signdness detection of expressions with bit- and part-selects	Clifford Wolf	2014-07-28
*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Fixed two memory leaks in ast simplify	Clifford Wolf	2014-07-25
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
*	Various small fixes (from gcc compiler warnings)	Clifford Wolf	2014-07-23
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
*	SigSpec refactoring: More cleanups of old SigSpec use pattern	Clifford Wolf	2014-07-22
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17
*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17
*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17
*	changes in verilog frontend for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16
*	Fixed processing of initial values for block-local variables	Clifford Wolf	2014-07-11
*	Fixed handling of mixed real/int ternary expressions	Clifford Wolf	2014-06-25
*	More found_real-related fixes to AstNode::detectSignWidthWorker	Clifford Wolf	2014-06-24