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Merge branch 'bugfix'
Clifford Wolf
2013-05-16
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Fixed synthesis of functions in latched blocks
Clifford Wolf
2013-05-16
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Fixed handling of positional module parameters
Clifford Wolf
2013-04-26
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Only use sha1 checksums for names of parametric modules when the verbose ↵
Clifford Wolf
2013-04-26
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form is to long
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Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵
Clifford Wolf
2013-04-13
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as case values
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Now only use value from "initial" when no matching "always" block is found
Clifford Wolf
2013-03-31
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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
Clifford Wolf
2013-03-31
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Implemented proper handling of stub placeholder modules
Clifford Wolf
2013-03-28
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Improvements and bugfixes for generate blocks with local signals
Clifford Wolf
2013-03-26
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Fixed handling of unconditional generate blocks
Clifford Wolf
2013-03-26
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Added nosync attribute and some async reset related fixes
Clifford Wolf
2013-03-25
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Added mem2reg option to verilog frontend
Clifford Wolf
2013-03-24
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Another fix in mem2reg ast simplify logic
Clifford Wolf
2013-03-24
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Improved mem2reg handling in ast simplifier
Clifford Wolf
2013-03-24
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Tiny fixes to verilog parser
Clifford Wolf
2013-03-23
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Moved stand-alone libs to libs/ directory and added libs/subcircuit
Clifford Wolf
2013-02-27
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Added support for verilog genblock[index].member syntax
Clifford Wolf
2013-02-26
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initial import
Clifford Wolf
2013-01-05