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* Added support for local regs in named blocksClifford Wolf2013-12-04
* Fixed temp net name generation in rtlil process generator for abbreviated nam...Clifford Wolf2013-11-28
* Added "src" attribute to processesClifford Wolf2013-11-28
* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-24
* Added verilog frontend -ignore_redef optionClifford Wolf2013-11-24
* Early wire/reg/parameter width calculation in ast/simplifyClifford Wolf2013-11-24
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Fixed async proc detection in mem2regClifford Wolf2013-11-21
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Another name resolution bugfix for generate blocksClifford Wolf2013-11-20
* Do not allow memory bit select on the left side of an assignmentClifford Wolf2013-11-20
* Fixed name resolution of local tasks and functions in generate blockClifford Wolf2013-11-20
* Implemented part/bit select on memory readClifford Wolf2013-11-20
* Fixed two bugs in mem2reg functionality in AST frontendClifford Wolf2013-11-18
* Added dumping of attributes in AST frontendClifford Wolf2013-11-18
* Fixed parsing of default cases when not last caseClifford Wolf2013-11-18
* Fixed mem2reg for reg usage outside always blockClifford Wolf2013-11-18
* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
* Call internal checker more oftenClifford Wolf2013-11-10
* More undef-propagation related fixesClifford Wolf2013-11-08
* Fixed handling of different signedness in power operandsClifford Wolf2013-11-08
* Implemented const folding of ternary op with undef selectClifford Wolf2013-11-08
* Fixed handling of power operatorClifford Wolf2013-11-07
* Fixed more extend vs. extend_u0 issuesClifford Wolf2013-11-07
* Disabled const folding of ternary op when select is undefClifford Wolf2013-11-07
* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-07
* Fixed sign handling in constantsClifford Wolf2013-11-07
* Fixed const folding in corner cases with parametersClifford Wolf2013-11-07
* Fixed width detection for replicate operatorClifford Wolf2013-11-07
* Fixed at_zero evaluation of dynamic rangesClifford Wolf2013-11-07
* Various fixes for correct parameter supportClifford Wolf2013-11-07
* Fixed the fix for propagation of width hints for $signed() and $unsigned()Clifford Wolf2013-11-07
* Fixed propagation of width hints for $signed() and $unsigned()Clifford Wolf2013-11-06
* Additional fixes for undef propagation in concat and replicate opsClifford Wolf2013-11-06
* Improved width extension with regard to undef propagationClifford Wolf2013-11-06
* Another fix for early width and sign detection in ast simplifierClifford Wolf2013-11-04
* Fixed const folding of ternary operatorClifford Wolf2013-11-04
* Use proper bit width ans sign extension for const foldingClifford Wolf2013-11-04
* Fixes for early width and sign detection in ast simplifierClifford Wolf2013-11-04
* further improved early width and sign detection in ast simplifierClifford Wolf2013-11-04
* Fixed detectSignWidthWorker (ast frontend) for AST_CONCATClifford Wolf2013-11-03
* Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...Clifford Wolf2013-11-02
* Various ast changes for early expression width detection (prep for constfold ...Clifford Wolf2013-11-02
* Fixed handling of boolean attributes (frontends)Clifford Wolf2013-10-24
* Added support for notif0/notif1 primitivesJohann Glaser2013-08-20
* Fixed width and sign detection for ** operatorClifford Wolf2013-08-19
* Added support for bufif0/bufif1 primitivesClifford Wolf2013-08-19
* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-19