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Author
Age
*
Some spelling errors fixed
Ruben Undheim
2019-10-18
*
New upstream version 0.9
Ruben Undheim
2019-10-18
*
Imported GIT HEAD: 0.8+20190328git32bd0f2
Ruben Undheim
2019-03-28
*
New upstream version 0.8
Ruben Undheim
2018-10-17
*
New upstream version 0.7+20181007git9850de4
Ruben Undheim
2018-10-15
*
New upstream version 0.7+20180830git0b7a184
Ruben Undheim
2018-08-30
*
Imported yosys 0.7
Ruben Undheim
2016-11-03
*
Squashed commit of the following:
Ruben Undheim
2016-09-23
*
Fixed some visual studio warnings
Clifford Wolf
2016-02-13
*
genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSi...
Rick Altherr
2016-01-31
*
Fixed handling of re-declarations of wires in tasks and functions
Clifford Wolf
2015-11-23
*
More bugfixes in handling of parameters in tasks and functions
Clifford Wolf
2015-11-12
*
Fixed handling of parameters and localparams in functions
Clifford Wolf
2015-11-11
*
Import more std:: stuff into Yosys namespace
Clifford Wolf
2015-10-25
*
Fixed complexity of assigning to vectors in constant functions
Clifford Wolf
2015-10-01
*
Fixed detection of unconditional $readmem[hb]
Clifford Wolf
2015-09-30
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Bugfixes in $readmem[hb]
Clifford Wolf
2015-09-25
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Fixed segfault in AstNode::asReal
Clifford Wolf
2015-09-25
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Added read-enable to memory model
Clifford Wolf
2015-09-25
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Fixed AstNode::mkconst_bits() segfault on zero-sized constant
Clifford Wolf
2015-09-24
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Bugfix in handling of multi-dimensional memories
Clifford Wolf
2015-09-23
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Warning for $display/$write outside initial block
Clifford Wolf
2015-09-23
*
Fixed multi-level prefix resolving
Clifford Wolf
2015-09-22
*
Improvements to $display system task
Andrew Zonenberg
2015-09-19
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Added AST_INITIAL checks for $finish and $display
Clifford Wolf
2015-09-18
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Initial implementation of $display()
Andrew Zonenberg
2015-09-18
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Initial implementation of $finish()
Andrew Zonenberg
2015-09-18
*
Fixed handling of memory read without address
Clifford Wolf
2015-08-22
*
Another block of spelling fixes
Larry Doolittle
2015-08-14
*
Keep gcc from complaining about uninitialized variables
Larry Doolittle
2015-08-14
*
Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
*
Added WORDS parameter to $meminit
Clifford Wolf
2015-07-31
*
Fixed nested mem2reg
Clifford Wolf
2015-07-29
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
*
Fixed handling of parameters with reversed range
Clifford Wolf
2015-06-08
*
Fixed signedness of genvar expressions
Clifford Wolf
2015-05-29
*
Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()
Clifford Wolf
2015-03-01
*
Added non-std verilog assume() statement
Clifford Wolf
2015-02-26
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Added deep recursion warning to AST simplify
Clifford Wolf
2015-02-20
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Parser support for complex delay expressions
Clifford Wolf
2015-02-20
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Convert floating point cell parameters to strings
Clifford Wolf
2015-02-18
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Various fixes for memories with offsets
Clifford Wolf
2015-02-14
*
Added "read_verilog -nomeminit" and "nomeminit" attribute
Clifford Wolf
2015-02-14
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Creating $meminit cells in verilog front-end
Clifford Wolf
2015-02-14
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Added AstNode::simplify() recursion counter
Clifford Wolf
2015-02-13
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Ignore explicit assignments to constants in HDL code
Clifford Wolf
2015-02-08
*
Fixed a bug with autowire bit size
Clifford Wolf
2015-02-08
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Added ENABLE_NDEBUG makefile options
Clifford Wolf
2015-01-24
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Ignoring more system task and functions
Clifford Wolf
2015-01-15
*
Fixed handling of "input foo; reg [0:0] foo;"
Clifford Wolf
2015-01-15
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