yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Fixed a bug in AST frontend for cases with non-blocking assigned variables as...	Clifford Wolf	2013-04-13
*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31
*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28
*	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26
*	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26
*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24
*	Another fix in mem2reg ast simplify logic	Clifford Wolf	2013-03-24
*	Improved mem2reg handling in ast simplifier	Clifford Wolf	2013-03-24
*	Tiny fixes to verilog parser	Clifford Wolf	2013-03-23
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27
*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26
*	initial import	Clifford Wolf	2013-01-05