yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Various small fixes (from gcc compiler warnings)	Clifford Wolf	2014-07-23
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
*	SigSpec refactoring: More cleanups of old SigSpec use pattern	Clifford Wolf	2014-07-22
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17
*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17
*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17
*	changes in verilog frontend for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16
*	Fixed processing of initial values for block-local variables	Clifford Wolf	2014-07-11
*	Fixed handling of mixed real/int ternary expressions	Clifford Wolf	2014-06-25
*	More found_real-related fixes to AstNode::detectSignWidthWorker	Clifford Wolf	2014-06-24
*	fixed signdness detection for expressions with reals	Clifford Wolf	2014-06-21
*	Added AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17
*	Improved handling of relational op of real values	Clifford Wolf	2014-06-17
*	Improved ternary support for real values	Clifford Wolf	2014-06-16
*	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	Clifford Wolf	2014-06-16
*	Added found_real feature to AstNode::detectSignWidth	Clifford Wolf	2014-06-16
*	Improved AstNode::realAsConst for large numbers	Clifford Wolf	2014-06-15
*	Improved AstNode::asReal for large integers	Clifford Wolf	2014-06-15
*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14
*	Fixed relational operators for const real expressions	Clifford Wolf	2014-06-14
*	Added support for math functions	Clifford Wolf	2014-06-14
*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14
*	Implemented more real arithmetic	Clifford Wolf	2014-06-14
*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14
*	Added real->int convertion in ast genrtlil	Clifford Wolf	2014-06-14
*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13
*	Add support for cell arrays	Clifford Wolf	2014-06-07
*	Added support for repeat stmt in const functions	Clifford Wolf	2014-06-07
*	further improved const function support	Clifford Wolf	2014-06-07
*	improved const function support	Clifford Wolf	2014-06-06
*	fix functions with no block (but single statement, loop, etc.)	Clifford Wolf	2014-06-06
*	improved ast simplify of const functions	Clifford Wolf	2014-06-06
*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06
*	Include id2ast pointers when dumping AST	Clifford Wolf	2014-03-05
*	Fixed merging of compatible wire decls in AST frontend	Clifford Wolf	2014-03-05
*	Bugfix in recursive AST simplification	Clifford Wolf	2014-03-05
*	Fixed bit-extending in $mux argument (use $bu0 instead of $pos)	Clifford Wolf	2014-02-26
*	Don't blow up constants unneccessarily in Verilog frontend	Clifford Wolf	2014-02-24
*	Fixed bug in generation of undefs for $memwr MUXes	Clifford Wolf	2014-02-22
*	Cleanups in handling of read_verilog -defer and -icells	Clifford Wolf	2014-02-20
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17
*	Improved support for constant functions	Clifford Wolf	2014-02-16
*	Correctly convert constants to RTLIL (fixed undef handling)	Clifford Wolf	2014-02-15
*	Be more conservative with new const-function code	Clifford Wolf	2014-02-14
*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14